Texas Instruments Corporation

Mitsubishi Denki Kabushiki Kaisha

Lee Alan Larson

Henry R Hoar

Gary L Swoboda

Gilbert Laurenti

Douglas E Deao

Mark B Rix

Roland R Hoar

Huimin Xu

An electronic circuit includes a first processor () operable to perform processing operations, a first trace buffer () coupled to the first processor (), a first triggering circuit () coupled to the first processor (), the first triggering circuit () operable to detect a specified sequence of particular processing operations in the first processor (); a second processor (), a second trace buffer () coupled to the second processor (), a second triggering circuit () coupled to the second processor (), the second triggering circuit () operable to detect at least one other processing operation in the second processor (); and a cross trace circuit () having a trace output and having inputs coupled to the first triggering circuit () and to the second triggering circuit (), the cross trace circuit () configurably operable to respond to a sequence including both a detection of the sequence of particular processing operations of the first processor () by the first triggering circuit () and a detection of the at least one other processing operation of the second processor () by the second triggering circuit (), to couple at least one of the first trace buffer () and the second trace buffer () to the trace output. Various circuits, devices, telecommunications products, wireless handsets, systems and processes of operation and manufacture are disclosed.

Circuits, systems, apparatus and processes for monitoring activity in multi-processing systems

In a JTAG test and debug environment, the signal groups for boundary scans can have several lengths including signal groups that are longer that the shift register out. A storage unit is provided with a plurality of storage location lengths. The boundary scan signal groups are stored in a location having a suitable storage capacity. The command that transfers the boundary scan signal group includes a parameter identifying the relevant location. The scan control unit, upon receiving the command, transfers the entire boundary scan signal group as a result this command even if several transfers through the shift register out are required.

Apparatus and method for transferring multiple scan length signal groups for JTAG boundary scans

A system comprising a system under test (SUT) having a control logic. The SUT further comprises testing logic coupled to the SUT and adapted to provide to the SUT a clock signal to facilitate communications between the testing logic and the SUT. The control logic monitors a number of activated processors in a scan chain coupled to the control logic. If the number of activated processors is reduced, the control logic dynamically decreases a frequency of the clock signal.

Dynamic frequency scaling for JTAG communication

In a test and debug environment using a JTAG protocol to test a target processing unit, apparatus for multi-value polling permits a poll unit, associated with the scan controller, to determine whether one of several possible signal groups is present in the received data stream. The test and debug unit generates a series of numbers, each number corresponding to a preselected signal groups. The corresponding field in the received data stream is decoded to provide a series of output signals, each output signal corresponding to one group. The output signals of the decoder are compared to corresponding numbers of the expected value. When a signal from the decoder unit is found to correspond to one of the selected data number, the poll operation is a success.

Apparatus and method for performing a multi-value polling operation in a JTAG data stream

In a multi processor environment wherein the processors are capable of implementing a streaming data mode of operation, a technique is provided that reduces the number of bits shifted through the scan chain necessary to select a processor for operating in the streaming data mode. All test control device associated with the processor have an instruction entered therein. After execution of the instruction, all of the processors are entered in a bypass mode of operation. Then, a logic '0' in the bypass register will cause the associated target processor to enter the streaming data mode, while a logic '1' in the bypass register will cause the processor to enter the bypass mode. To select a new target processor, logic &#x201c;1&#x201d;s in the bypass register will reset the test control unit and thereafter the entry of a logic &#x201c;1&#x201d; will cause the non-target processors to enter the bypass mode, while a logic &#x201c;0&#x201d; in a bypass register will select the new target processor (i.e., for operating in the streaming data mode).

Apparatus and method for device selective scans in data streaming test environment for a processing unit having multiple cores

In a JTAG test and debug environment, the parameters that are accessed by command include a delay parameter. The delay parameter prevents the subsequent command from being executed until both the original command has been executed and the clock cycles indicated by the delay parameter have been completed. Because the time delay is included as a parameter identified by the command, the delay parameter can be programmed.

Apparatus and method for using variable end state delay to optimize JTAG transactions

A method for debugging a target processor is provided that includes storing a plurality of data values to be sent to the target processor in a first-in first-out (FIFO) buffer unit, saving a copy of an address in a read address counter of the FIFO buffer unit, wherein the address is that of an initial data value of a sequential portion of the plurality of data values, performing a transfer operation to send the sequential portion to the target processor, wherein the read address counter is incremented as each data value is sent. The method also includes resetting the read address counter with the copy of the address if the transfer operation fails and performing the transfer operation again.

Apparatus and method for performing speculative reads from a scan control unit using FIFO buffer units

A reconfigurable cable/pod unit replaces the cable/pod unit coupling an emulation unit and a target processor. The reconfigurable cable/pod unit includes the discrete logic elements, a programmable unit and interface logic. The programmable unit and the interface unit permit the pod unit to assign conductors to the coupled cable. The interface unit includes storage and other logic elements that compensate for the differences in clock speeds and in rates of data exchange between the emulation unit and the target processor. No changes are necessary in the emulation unit to use the reconfigurable cable/pod unit. The reconfigurable cable pod unit permits, by changing the programming in the programmable unit, to operate in selectable modes, to provide a selectable interface to the target processor, to implement changes and upgrades in the testing procedures, and to test different types of target processors.

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Katy, TX, United States of America

Lee Alan Larson