Src Computers, Inc.

Cray Computer Corporation

Fg Src, LLC

Src Labs, LLC

Lee A Burton

Jon M Huppenthal

Thomas R Seeman

David E Caliga

Timothy J Tewalt

Jonathan L Bertoni

A multi-processor computer architecture incorporating distributed multi-ported common memory modules wherein each of the memory modules comprises a control block functioning as a cross-bar router in conjunction with one or more associated memory banks or other data storage devices. Each memory module has multiple I/O ports and the ability to relay requests to other memory modules if the desired memory location is not found on the first module. A computer system in accordance with the invention may comprise memory module cards along with processor cards interconnected using a baseboard or backplane having a toroidal interconnect architecture between the cards.

Multi-processor computer architecture incorporating distributed multi-ported common memory modules

An enhanced switch/network adapter port incorporating shared memory resources ('SNAPM&#x2122;') selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module ('FB-DIMM') format for clustered computing systems employing direct execution logic such as multi-adaptive processor elements (&#x201c;MAP&#xae;&#x201d;, all trademarks of SRC Computers, Inc.). Functionally, the SNAPM modules incorporate and properly allocate memory resources so that the memory appears to the associated dense logic device(s) (e.g. a microprocessor) to be functionally like any other system memory such that no time penalties are incurred when accessing it. Through the use of a programmable access coordination mechanism, the control of this memory can be handed off to the SNAPM memory controller and, once in control, the controller can move data between the shared memory resources and the computer network such that the transfer is performed at the maximum rate that the memory devices themselves can sustain. This provides the highest performance link to the other network devices such as MAP&#xae; elements, common memory boards and the like.

Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM)

A switch/network adapter port ('SNAP&#x2122;') in a dual in-line memory module ('DIMM') or Rambus&#x2122; in-line memory module (&#x201c;RIMM&#x201d;) format for clustered computers employing multi-adaptive processor (&#x201c;MAP&#xae;&#x201d;, both trademarks of SRC Computers, Inc.) elements for use with interleaved memory controllers. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format adapter port coupled to a reconfigurable processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (&#x201c;AGP&#x201d;) or system maintenance (&#x201c;SM&#x201d;) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (&#x201c;FPGA&#x201d;) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.

Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers

An enhanced switch/network adapter port ('SNAP&#x2122;') including collocated shared memory resources ('SNAPM&#x2122;') in a dual in-line memory module (&#x201c;DIMM&#x201d;) or any other memory module format for clustered computing systems employing direct execution logic such as multi-adaptive processor elements (&#x201c;MAP&#xae;&#x201d;, all trademarks of SRC Computers, Inc.). Functionally, the SNAPM modules incorporate and properly allocate memory resources so that the memory appears to the associated dense logic device(s) (e.g. a microprocessor) to be functionally like any other system memory such that no time penalties are incurred when accessing it. Through the use of a programmable access coordination mechanism, the control of this memory can be handed off to the SNAPM memory controller and, once in control, the controller can move data between the shared memory resources and the computer network such that the transfer is performed at the maximum rate that the memory devices themselves can sustain. This provides the highest performance link to the other network devices such as MAP&#xae; elements, common memory boards and the like.

Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices

A switch/network adapter port ('SNAP') for clustered computers employing multi-adaptive processor ('MAP&#x2122;', a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (&#x201c;DIMM&#x201d;) or Rambus&#x2122; in-line memory module (&#x201c;RIMM&#x201d;) format to significantly enhance data transfer rates over that otherwise available through use of the standard peripheral component interconnect (&#x201c;PCI&#x201d;) bus. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (&#x201c;AGP&#x201d;) or system maintenance (&#x201c;SM&#x201d;) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (&#x201c;FPGA&#x201d;) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.

Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format

A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port ('APIP') added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses to and from this port, as well as the main microprocessor bus, are then arbitrated by the memory control circuitry forming a portion of the controller chip. In this fashion, both the microprocessors and the adaptive processors of the hybrid computing system exhibit equal memory bandwidth and latency. In addition, because it is a separate electrical port from the microprocessor bus, the APIP is not required to comply with, and participate in, all FSB protocol. This results in reduced protocol overhead which results higher yielded payload on the interface.

Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port

A computing system having at least one microprocessor and a memory subsystem coupled to the at least one microprocessor. A memory controller is coupled to manage memory transactions between the memory subsystem and the at least one microprocessor. At least one arbitration port is coupled to the memory controller and configured to receive an external arbitration signal.

System and method for providing an arbitrated memory bus in a hybrid computing system

A system and method for enhancing the utilization of available bandwidth for an uncached device. Data written to the device is done so by striding the available data into multiple data elements of the appropriate size for the uncached device. Data read from the device is retrieved from multiple addresses on the uncached device to avoid unnecessary waits cycles in the processor.

Bandwidth enhancement for uncached devices

A split directory-based cache coherency technique utilizes a secondary directory in memory to implement a bit mask used to indicate when more than one processor cache in a multi-processor computer system contains the same line of memory which thereby reduces the searches required to perform the coherency operations and the overall size of the memory needed to support the coherency system. The technique includes the attachment of a &ldquo;coherency tag&rdquo; to a line of memory so that its status can be tracked without having to read each processor's cache to see if the line of memory is contained within that cache. In this manner, only relatively short cache coherency commands need be transmitted across the communication network (which may comprise a Sebring ring) instead of across the main data path bus thus freeing the main bus from being slowed down by cache coherency data transmissions while removing the bandwidth limitations inherent in other cache coherency techniques. The technique disclosed may be further expanded to incorporate the &ldquo;bus lock&rdquo; capability of bus-based systems compatible with the requirements for multi-processor synchronization.

Split directory-based cache coherency technique for a multi-processor computer system

A duty cycle control circuit, and an associated method, generates an output clock signal having a duty cycle which differs by a desired amount with the duty cycle of an input clock signal. Offset bias signal circuitry generates an offset bias signal which offsets a copy clock signal and an inverted copy clock signal relative to one another by a selected offset bias. The duty cycle of the output clock signal differs with the duty cycle of the input clock signal by an amount which is related to the amplitude of the offset bias signal.

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Divide, CO, United States of America

Lee A Burton