International Business Machines Corporation

Amazon Technologies, Inc.

Other

Leah Shalev

Nafea Bshara

Georgy Machulsky

Zorik Machulsky

Giora Biran

Erez Izenberg

Vadim Makhervaks

Renato John Recio

Richard Louis Arndt

Jaya Srikrishnan

Harvey Gene Kiel

Julian Satran

David Darden Chambliss

Ehood Garmiza

Ilan Shimony

Brian William Barrett

Ron Diamant

Shmuel Ben-Yehuda

Constantine Gavrilov

Guy Nakibly

Adi Habusha

Patrick Allen Buckland

Thomas Basil Smith, Iii

Eliyahu Weissbrem

Saar Gross

Alexander Matushevsky

Ton Engbersen

Jan Leonard Camenisch

Norbert Paul Kusters

Michael Waidner

Igor Chirashnya

Michael Backes

Eric Jason Brandwine

David R Richardson

Marc John Brooker

Danny Wei

Edward Joseph Seminaro

James Xenidis

Said Bshara

Avigdor Segal

Nachiappan Arumugam

John Luther Guthrie, Ii

Christopher Nathan Watson

Eyal Lotem

Michael Steven Siegel

Alan Frederic Benner

Gregory Scott Still

Orran Yaakov Krieger

Orit Luba Wasserman

Jonathan Cohen

Edi Shmueli

Shlomit Sarah Pinter

Ben-Ami Yassour

Hani Ayoub

Noam Katz

Claudiu Schiller

Kirill Shoikhet

Shadi Ammouri

Scott D Guthridge

Nofar Mann

George Machulsky

Rotem Shaanan

Yehuda Yitschak

Yossi Leybovich

Saleh Abd-Alhaleem

Shyam Prasad Rajagopal

Ehab Wattad

Rony Ross

Nick Rash

Vadim Makher-Vaks

Vadim Ibm Uk Ltd Ip Law Makhervaks

Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network. In one example, RDMA functionality is provided by combining a host executing instructions for RDMA software applications with dedicated hardware accelerator, where the host has access to substantially all RDMA connection context (e.g., configuration, status, state machine, counters, etc.) and a hardware accelerator stores a portion of the context information for a set of currently active transactions. The hardware accelerator derives a transaction identifier from header information in received RDMA packets and performs a local RDMA operation using at least a portion of the received data, a destination address of the location RDMA operation being based at least in part on a memory address determined using the transaction identifier.

Transaction based remote direct memory access

Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network according to a number of different RDMA protocols. In one example, a method includes receiving remote direct memory access (RDMA) packets via a network adapter, deriving a protocol index identifying an RDMA protocol used to encode data for an RDMA transaction associated with the RDMA packets, applying the protocol index to a generate RDMA commands from header information in at least one of the received RDMA packets, and performing an RDMA operation using the RDMA commands.

Flexible remote direct memory access

Systems and methods are provided to reduce the latency in accessing an input/output (I/O) hardware register by software executing on a central processing unit (CPU). The hardware register is located in a controller coupled to the CPU via an I/O bus. The CPU software can send a command to the controller for execution. The controller can execute the command and update the hardware register to indicate that the command has been executed. The controller can write contents of the hardware register to a specified address in a CPU memory that is assigned by the CPU software. The CPU software can read the specified address to determine that the command has been executed instead of reading the hardware register on the I/O bus.

Input/output (I/O) register reflected in CPU memory

A technique for remote direct memory access (RDMA) may include receiving a packet that was sent over a network, and determining the packet has metadata used for queue selection. The technique may also include selecting a queue based on the metadata, and writing the data of the packet to an application memory using the datapath associated with the selected queue. Amended metadata can be generated to indicate that the data has been written to the application memory, and the amended metadata can be stored in a software accessible buffer.

Hybrid remote direct memory access

Communication in an asymmetric multiengine system is handled using engine routing tables defining subsets of engines to control engine-to-engine connection mapping. Local devices perform an engine selection process that includes selecting an engine routing table based on a number of remote engines in a remote device and selecting an engine set from the selected table based on an identifier of the remote device. A connection to the remote device is created using the engines identified in the selected engine set.

Symmetric communication for asymmetric environments

An integrated circuit device includes a packet type detection circuit, a security circuitry, and a configuration circuit. The packet type detection circuit is operable to determine a packet type of a packet based on header portions of the packet. The security circuit is operable to perform security processing of the packet according to a set of security parameters. The configuration circuit operable to determine the set of security parameters based on the packet type of the packet, an identifier associated with the packet, and an index associated with the packet, and provide the set of security parameters to the security circuit.

Hardware security accelerator

Provided are systems and methods for reliable, out-of-order transmission of packets. In some implementations, provided is an apparatus configured to communicate with a network and a host device. The apparatus may receive out-of-order packets from a remote device. The apparatus may transmit selective-acknowledgements to the remote device such that remote device can retransmit certain packets. The out-of-order packets can be provided to software for re-ordering.

Reliable, out-of-order transmission of packets

A hardware security accelerator includes a configurable parser that is configured to receive a packet and to extract from the packet headers associated with a set of protocols. The security accelerator also includes a packet type detection unit to determine a type of the packet in response to the set of protocols and to generate a packet type identifier indicative of the type of the packet. A configurable security unit includes a configuration unit and a configurable security engine. The configuration unit configures the configurable security engine according to the type of the packet and to content of at least one of the headers extracted from the packet. The configurable security engine performs security processing of the packet to provide at least one security result.

Disclosed herein is a method including receiving, from a user application, data to be transmitted from a source address to a destination address using a single connection through a network; and splitting the data into a plurality of packets according to a communication protocol. For each packet of the plurality of packets, a respective flowlet for the packet to be transmitted in is determined from a plurality of flowlets; a field in the packet used by a network switch of the network to route the packet is set based on the determined flowlet for the packet; and the packet is sent via the determined flowlet for transmitting through the network.

Multi-path transport design

A data storage system includes multiple head nodes and data storage sleds. The data storage sleds include multiple mass storage devices and a sled controller. Respective ones of the head nodes are configured to obtain credentials for accessing particular portions of the mass storage devices of the data storage sleds. A sled controller of a data storage sled determines whether a head node attempting to perform a write on a mass storage device of a data storage sled that includes the sled controller is presenting with the write request a valid credential for accessing the mass storage devices of the data storage sled. If the credentials are valid, the sled controller causes the write to be performed and if the credentials are invalid, the sled controller returns a message to the head node indicating that it has been fenced off from the mass storage device.

Data storage system with enforced fencing

A technique for packet processing may include maintaining a data structure representing transport status information associated with a sliding window of sequential packets for a host system. When a packet targeted for the host system is received, a packet validation process can be performed on the packet. The packet validation process may include validating that the packet belongs to the sliding window of the sequential packets by comparing the packet serial number of the packet against the packets being expected in the sliding window. The packet validation process may also include validating that the packet is being received for the first time and is not a duplicate packet. Upon validating the packet, the packet can be placed into the host system, and the status information can be updated to indicate that the packet has been received.

Packet serial number validation

Apparatus, methods, and computer-readable storage media are disclosed for core-to-core communication between physical and/or virtual processor cores. In some examples of the disclosed technology, application cores write notification data (e.g., to doorbell or PCI configuration memory space accesses via a memory interface), without synchronizing with the other application cores or the service cores. In one examples of the disclosed technology, a message selection circuit is configured to, serialize data from the plurality of user cores by: receiving data from a user core, selecting one of the service cores to send the data based on a memory location addressed by the sending user core, and sending the received data to a respective message buffer dedicated to the selected service core.

Core-to-core communication

Growing community of inventors

Zichron-Yaakov, Israel

Leah Shalev