Shenzhen Intellifusion Technologies Co., Ltd.

Zte Corporation

Lea Hwang Lee

Wei Li

Qingxin Cao

Wen Hao Jiang

Chunyu Tian

Hui Ren

Heguo Wang

Dan Zhang

An image processing method is configured to split a deconvolution kernel according to a preset splitting mode to obtain a sub-convolution kernel. And then, determining an original sub-matrix corresponding to the sub-convolution kernel, according to parameters of the sub-convolution kernel and an image feature matrix, and performing a convolution operation on the original sub-matrix corresponding to the sub-convolution kernel by using the sub-convolution kernel to obtain a deconvolution sub-matrix corresponding to each sub-convolution kernel; determining a target feature matrix according to the deconvolution sub-matrix corresponding to the sub-convolution kernel. When performing the deconvolution operation by the method, the image feature matrix doesn't need to perform tic-tac-toe filling to reduce a storage space occupied in the deconvolution operation process; in addition, since zero filled in the tic-tac-toe isn't participated in the deconvolution operation, calculation amount can be greatly reduced, and calculation efficiency of the deconvolution operation can be improved.

Image processing method, image processing device, electronic equipment and computer readable storage medium

A neural network chip and a related product are provided. The neural network chip () includes: a memory (), a data reading/writing circuit, a convolution calculation circuit, wherein the memory is used for storing a feature map; the data reading/writing circuit is used for reading the feature map from the memory and execute an expansion and zero-padding operation on the feature according to configuration information of the feature map, and sending to the convolution calculation circuit (S); and the convolution calculation circuit is used for performing convolution calculation on the data obtained after the expansion and zero-padding operation to implement a de-convolution operation (S). The technical solution has advantages of saving memory usage and bandwidth.

Neural network chip, method of using neural network chip to implement de-convolution operation, electronic device, and computer readable storage medium

Provided are a data transmission method for a neural network, and a related product. The method includes the following steps: acquiring a weight specification of weight data stored in a memory, comparing the weight specification with a specification of a write memory in terms of size and determining a comparison result; according to the comparison result, dividing the write memory into a first-in first-out write memory and a multiplexing write memory; according to the comparison result, determining data reading policies of the first-in first-out write memory and the multiplexing write memory; and according to the data reading policies, reading weights from the first-in first-out write memory and the multiplexing write memory and loading the weights to a calculation circuit. The technical solution provided by the present application has the advantages of low power consumption and short calculation time.

Data transmission method and calculation apparatus for neural network, electronic apparatus, computer-readable storage medium and computer program product

The disclosure provides a device for implementing address buffer management of a processor, including: an assembler configured to perform operations to obtain intermediate values when the assembler encodes a set instruction for an address automatic-increment value and boundary values, and to encapsulate the intermediate values into the set instruction for the address automatic-increment value and boundary values; and a processor configured to determine, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation, so as to achieve the address buffer management. The disclosure also provides a method for implementing address buffer management of a processor, including: a processor decodes a set instruction for an address automatic-increment value and boundary values to obtain intermediate values, and determines, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation when the processor performs a load or store instruction, so as to realize the address buffer management. Through the device and the method of the disclosure, the hardware costs of the processor are reduced and design requirements of the processor's time sequence and energy efficiency are met.

Growing community of inventors

Shenzhen, China

Lea Hwang Lee