Freescale Semiconductor,inc.

Motorola Corporation

Lea Hwang Lee

William C Moyer

John H Arends

Jeffrey William Scott

Afzal M Malik

A system and methods are discussed for providing additional capabilities to some instructions associated with loop execution. A standard set of instructions is processed using only a standard instruction size. Some loop instructions are processed with a standard instruction portion of the standard instruction size and an augmented instruction portion. The augmented instruction portion provides additional capabilities associated with the standard instruction portion. The augmented instruction portion can provide capabilities associated with conditional execution of the standard instruction portion or other instructions within a program loop. Furthermore, the augmented instruction portion can provide an additional operand to be used with the standard instruction portion.

System for expanded instruction encoding and method thereof

In one embodiment, a data processing system () includes a first master, storage circuitry () coupled to the first master () for use by the first master (), a first control storage circuit () which stores a first prefetch limit (), a prefetch buffer (), and prefetch circuitry () coupled to the first control storage circuit, to the prefetch buffer, and to the storage circuitry. In one embodiment, the prefetch circuitry () selectively prefetches a predetermined number of lines from the storage circuitry into the prefetch buffer () based on whether or not a prefetch counter, initially set to a value indicated by the first prefetch limit, has expired. In one embodiment, the first prefetch limit may therefore be used to control how many prefetches occur between misses in the prefetch buffer.

Prefetch control in a data processing system

A method for processing scalar and vector executions, where vector executions may be &ldquo;true&rdquo; vector operations, CVA, or pseudo-vector operations, PVA. All three types of executions are processed using one architecture. In one embodiment, a compiler analyzes code to identify sections that are vectorizable, and applies either CVA, PVA, or a combination of the two to process these sections. Register overlay is provided for storing load address information and data in PVA mode. Within each CVA and PVA instruction, enable bits describe the data streaming function of the operation. A temporary memory, TM, accommodates variable size vectors, and is used in vector operations, similar to a vector register, to store temporary vectors.

Method and apparatus for instruction execution in a data processing system

Embodiments of the present invention relate generally to data processing systems having instruction folding and methods for controlling execution of a program loop. One embodiment includes detecting execution of a program loop and prefetching data in response to detecting execution of the program loop. Another embodiment includes detecting execution of a program loop and scanning the program loop for remote independent instructions or data dependencies during at least one iteration. Another embodiment includes detecting execution of a program loop and storing intra-loop data dependency information in a dependency bit vector, and using the dependency bit vector to select at least one local independent instruction available for folding. One embodiment includes an instruction folding unit comprising a first controller, a second controller, and a storage unit coupled to the second controller. Another embodiment includes a data processing system comprising a validation counter and a storage unit coupled to the validation counter where the storage unit includes a dependency bit vector corresponding to instructions of a program loop.

Data processing system having instruction folding and method thereof

A specific implementation is disclosed where a backward branch address instruction is fetched at a branch address. The backward branch instruction has an offset value to define the size of a program loop. A counter is set to a value that is proportional to the size of the loop. In one example the counter is set to the offset value. As each instruction of the loop is executed the counter is modified to indicate a remaining number of instructions in the loop. When no instructions remain in the current pass of the loop, the counter is reset to the offset value and the loop is repeated until a termination condition encountered. As part of the implementation the instruction after the branch instruction is read and stored prior to the loop being executed.

Data processor system having branch control and method thereof

A loop cache (26) is used in a data processing system for supplying instructions to a CPU to avoid accessing a main memory. Whether instructions stored in the loop cache can be supplied to the CPU is determined by a distributed TAG associated with the instruction address computed by the CPU. The instruction address includes an LCACHE index portion (42), an ITAG portion (44), and a GTAG (46). LCACHE index (42) selects corresponding locations in each of an ITAG array (50), an instruction array (52), and a valid bit array (54). A stored GTAG value (48) is chosen irrespective of where LCACHE index (42) is pointing. The GTAG portion of the instruction address (40) is compared to the stored GTAG value (48). The ITAG portion (44) of instruction address (40) is compared with the indexed ITAG of the ITAG array (50). If both the GTAG and ITAG compare favorably, the instruction is supplied from the loop cache to the CPU, rather than from main memory.

Distributed tag cache memory system and method for storing data in the

A data processing system (20) has a cache (26) that does not use a TAG array for storing a TAG address as in a conventional cache. The cache (26), according to one embodiment, uses a state machine (30) for transitioning the cache (26) to an active state in response to a change of flow instruction which is a short backward branch instruction of a predetermined displacement. The predetermined displacement is less than the number of entries in the cache (26), so the cache can remain active as long as the program is in a loop which can be contained entirely within the cache. A look ahead feature for the valid bit array is provided that associates the valid bit for a current instruction with a previous instruction, such that during a read of the cache, the valid bit for a next instruction is checked with the same index used to read the current instruction.

Growing community of inventors

Austin, TX, United States of America

Lea Hwang Lee