Lucent Technologies Inc.

Le Tieu Ly

Hon Shing Lau

Ravi Kumar Kolagotla

Jiancheng Mo

Hosahalli R Srinivas

Feng Chen

Ronald L Feiller

A flag generating circuit that uses a feedback mechanism to set or reset a flag associated with two systems with asynchronous clocks is provided. Upon receipt of a set flag (or reset flag) signal, the circuit immediately isolates the signal after setting (or resetting) the flag to prevent race conditions between the systems. The clock associated with the setting system is synchronously started when waiting to set the flag and synchronously stopped when waiting for the flag to be reset. The clock associated with the resetting system is synchronously started when waiting to reset the flag and synchronously stopped when waiting for the flag to be set. Accordingly, the flag generating circuit provides a race free and technology independent flag generating circuit capable of setting and resetting flags associated with asynchronous

Race free and technology independent flag generating circuitry

An integrated circuit having a fast carry generation adder for adding together two input signals has an initial stage and two or more intermediate stages. The adder may also include a final stage. Each intermediate stage has a carry mux and these carry muxes are grouped together, for example, adjacent to the initial stage and adjacent to the first intermediate stage. By grouping the carry muxes together, for example, in a column below the initial stage, the fast carry generation adder may be both faster and smaller than conventional adders and may reduce or even eliminate the need for any buffering between successive carry muxes.

Fast carry generation adder having grouped carry muxes

An integrated circuit including a circuit for determining shift overflow in a binary digital circuit having an n-bit shift data and an m-bit shift amount. The device has a logic array for producing an n-bit output from the m-bit shift amount; a conversion circuit for selectively converting the sign of an n-bit shift data; and a combination of OR and AND logical gates for logically combining the selectively converted n-bit shift data and the n-bit output producing an overflow output.

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Le Tieu Ly