United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Taiwan Memory Company

Nan Ya Technology Corporation

Taiwan Memory Corporation

Le-Tien Jung

Ming-Jing Ho

Yung-Chang Lin

Yukihiro Nagai

Tai-Sheng Feng

Nan-Ray Wu

Shih-Fang Tzou

Chin-Lung Lin

Chien-Ting Ho

Ying-Chiao Wang

Hung-Lin Shih

Ming-Tsung Chen

Shih-Fan Kuan

Po-Hung Chen

Harn-Jiunn Wang

Kirk Hsu

Li-Wei Liu

Hsuan-Tung Chu

Yo-Yi Gong

Chuck Chen

Shih-Kuei Yen

Ming-Che Li

Guan-Yi Liou

Huai-Jin Hsing

A flash includes a substrate comprising an active region and two electron storage structures disposed at two sides of the active region, wherein each of the electron storage structures comprises a silicon oxide/silicon nitride/silicon oxide composite layer. A buried gate is embedded in the active region, wherein the buried gate only consists of a control gate and a gate dielectric layer, and the gate dielectric layer is formed by a single material. Two source/drain doping regions are disposed in the active region at two sides of the buried gate.

DRAM and flash structure and method of fabricating the same

A semiconductor device includes a substrate having a cell region and a peripheral region, a thyristor on the cell region, a MOS transistor on the peripheral region, and a first silicide layer on the substrate adjacent to the thyristor on the cell region. Preferably, the thyristor includes: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the cell region, vertical dielectric patterns in the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer, and first contact plugs on the fourth semiconductor layer.

Semiconductor device having thyristor and metal-oxide semiconductor transistor

A semiconductor device includes: a substrate having a cell region and a peripheral region; a thyristor on the cell region; a MOS transistor on the peripheral region; a first shallow trench isolation (STI) between the thyristor and the MOS transistor; and a second STI between the first STI and the MOS transistor. The thyristor further includes: a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the cell region; patterned metal layers in the first semiconductor layer; vertical dielectric patterns on the patterned metal layers; and first contact plugs on the fourth semiconductor layer.

A method for fabricating a semiconductor device includes the steps of: providing a substrate having a cell region and a peripheral region; forming a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer on the substrate; forming a thyristor on the cell region; removing the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer on the peripheral region; and forming a metal oxide semiconductor (MOS) transistor on the peripheral region.

Method of integrating thyristor and metal-oxide semiconductor transistor on a semiconductor substrate

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of active areas, and an isolation structure. The substrate has a device region and a peripheral region surrounding the device region. The active areas are located in the substrate in the device region. When viewed from above, the edges of the ends of the active areas adjacent to the boundary of the device region are aligned with each other, and the width of the ends of the active areas adjacent to the boundary of the device region is greater than the width of the other portions of the active areas. The isolation structure is disposed in the substrate and surrounds the active areas and is located in the peripheral region.

Semiconductor device and manufacturing method thereof

A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.

Method of manufacturing flash memory cell

The embodiment provides a buried bit line process and scheme. The buried bit line is disposed in a trench formed in a substrate. The buried bit line includes a diffusion region formed in a portion of the substrate adjacent the trench. A blocking layer is formed on a portion sidewall of the trench. A conductive plug is formed in the trench, covering sidewalls of the diffusion region and the blocking layer.

Buried bit line process and scheme

A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench formed therein, forming a firs conductive layer on the substrate blanketly, forming a patterned photoresist having a surface lower than an opening of the trench in the trench, removing the first conductive layer not covered by the patterned photoresist to form a second conductive layer having a top lower than an opening of the trench in the trench, removing the patterned photoresist, performing a dry etching process to remove the second conductive layer from the bottom of the trench to form a third conductive layer on the sidewalls of the trench, performing a selective metal chemical vapor deposition to form a metal layer having a surface lower than a surface of the substrate, and forming a protecting layer filling the trench on the metal layer.

Manufacturing method for a buried circuit structure

A manufacturing method for a buried circuit structure includes providing a substrate having at least a trench therein, forming a conductive layer having a top lower than an opening of the trench in the trench, performing a selective metal chemical vapor deposition (CVD) to form a metal layer having a top lower than the substrate in the trench, and forming a protecting layer filling the trench on the metal layer.

A method of fabricating a storage node with a supported structure is provided. A dielectric stacked comprising an etch stop layer, a first dielectric layer, a support layer and a second dielectric layer is formed on a substrate. An opening is etched into the dielectric stacked. A conductive layer is formed on the second dielectric layer and inside the opening. The conductive layer directly above the second dielectric layer is removed to form columnar node structure. The second dielectric layer is then removed. A spacer layer is deposited on the support layer and the columnar node structure. A tilt-angle implant is performed to implant dopants into the spacer layer. The undoped spacer layer is removed to form a hard mask. The support layer not covered by the hard mask is etched away to expose the first dielectric layer. The first dielectric layer and the hard mask are removed.

Method of fabricating storage node with supported structure of stacked capacitor

A test key structure includes a substrate, a closed loop, a plurality of spacers, a plurality of first and second doping regions and a plurality of contacts. The closed loop having two conductive lines and two connection portions is located on the substrate. Each connection portion connects to one end of the conductive line and surrounds a contact region. The spacers are disposed at the edge of the closed loop to cover the substrate between the conductive lines. The first doping regions are located in the substrate outside the closed loop and the spacers. The second doping regions are located in the substrate under the spacers. The contacts are electrically connected to the first doping regions within the contact regions. Because the spacers and the conductive lines are incorporated into a test key structure, the influence of spacers upon the entire device can be more accurately determined.

Test key structure

A method for preventing polycide gate spiking, which essentially comprises the following steps: forms an oxide layer on a substrate; forming a polysilicon layer on the oxide layer; sputtering a barrier layer on the polysilicon layer; performing a first rapid thermal process; sputtering a silicide layer on the barrier layer; performing a photolithography process and an etching process to remove part of the silicide layer, part of the barrier layer and part of the polysilicon layer to form a polycide gate; and performing a second rapid thermal process. Further, as it is necessary to use both rapid thermal processes, the invention can be expanded such that only one rapid thermal process is applied. Both rapid thermal processes use almost no oxygen.

Method for preventing polycide gate spiking

A method of forming a triple well structure. A first photoresist layer is formed on a substrate having a first conductive type. A first ion implantation process is performed to form a first well, which has the first conductive type but a dopant concentration of the first well is higher than a dopant concentration of the substrate. The first photoresist layer is baked. A second ion implantation process is performed through the baked first photoresist layer to form a first doped region under the first well. The first doped region has a second conductive type. After removing the first photoresist layer, a second photoresist layer is formed on the substrate. A third ion implantation process is performed to form a second doped region in the substrate around the first well and to form a second well in the substrate. The second doped region and the second well have the second conductive type. The second doped region and the first doped region together surround the first well. The first doped region, the first well, and the second doped region compose a triple well structure.

Method for forming a triple well structure

A method of manufacturing a ROM cell. A DRAM cell is provided. An ONO (oxide-nitride-oxide) stacked layer is used as a dielectric film of a capacitor of the DRAM cell. When a supply power is over 6 volts, the dielectric layer would be breakdown so that leakage is occurred between a lower electrode and an upper electrode of the capacitor. The DRAM cell, which can be used as a ROM cell, is thus readout as a stock at fault to stock a logic state of &ldquo;1&rdquo; or &ldquo;0&rdquo;. The stored data as &ldquo;1&rdquo; or &ldquo;0&rdquo; is depended on voltage of the upper electrode (V ) and a voltage of the bit line (V ). If V >V , the breakdown of the dielectric film would make the cell stock at &ldquo;1&rdquo;, and a normal DRAM cell is stocked at &ldquo;0&rdquo;, and vice versa.

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Tainan, Taiwan

Le-Tien Jung