Quanta Computer Incorporated

Le-Sheng Chou

Sz-Chin Shih

Tien-Jung Chang

Wei-Yu Chien

Shuen-Hung Wang

Chao-Jung Chen

Wei-Yi Chu

Jui-Chi Huang

Wei-Ying Lu

A system and device for expanding accessible memory of a processor is provided. An interposer is coupled to the processor and a memory module. The interposer is coupled to a first connection and a second connection. The interposer includes a memory controller circuit. The memory controller circuit receives signals from the processor, using the first connection, and transmits the received signals to the memory module, using the second connection. The interposer expands memory access without an unnecessary second processor.

Systems and methods for expanding memory access

A system and method for providing efficient communication between a processor and a device. An interposer is provided to send signals from the processor to the device. The interposer includes a printed circuit board, a first interconnection port communicating with the processor, and a second interconnection port communicating with the device. A retimer/redriver circuit is coupled to the first interconnection port and the second interconnection port, and the retimer/redriver circuit routes signals from the first interconnection port to the second interconnection port.

Method and system for processor interposer to expansion devices

A system and method for generating a control bifurcation signal in accordance with the Open Compute Project (OCP) Specification. An OCP device is provided that has a bifurcation function with an input to activate a bus bifurcation function. An input/output control circuit having an output coupled to a bifurcation control line coupled to the OCP device is provided. The input/output control circuit is operable to provide a bifurcation control signal to the OCP device over the bifurcation control line during an auxiliary power phase transition period of powering-on the OCP device.

Control circuit for dynamic bifurcation control

The present disclosure provides flexible coupling of processor modules. An exemplary computing device, according to an embodiment of the present disclosure, can include a processor module with a plurality of processors and a plurality of module output ports associated with each processor. Each of the processors can include a plurality of chip communication channels (CCCs). The CCCs can be coupled to the module output ports of a first processor and can be coupled to other processors in the plurality of processors. The present disclosure additionally provides for a local mode or cooperative mode configuration. A local mode provides for a four-way connection between four processors and a cooperative mode provides for an eight-way connection between eight processors.

Flexible coupling of processor modules

A dual CMC structure is disclosed for a rack mounted structure. The structure has a first chassis with power supplies, a first chassis management controller, and a first set of network devices. A second chassis includes power supplies, a second chassis management controller and a second set of network devices. The respective chassis management controllers obtain status data of the power supplies, as well as status data from the other chassis management controllers. The first chassis management controller is designated as the master controller and reports the status data from both the first and second chassis. The structure is operable to change communication of the status data to the second chassis management controller, in the event the first chassis management controller fails.

CMC failover for two-stick canisters in rack design

Disclosed are a system, method, and computer-readable medium for optimizing a fan control system inside a rack system. In at least one example embodiment, the system can include a rack server with a plurality of chassis each having at least one node, each of the nodes including at least one adjustable air vent and configured for adjusting the at least one adjustable air vent based on an air flow requirement of the node. The system can further include a plurality of fans, where the plurality of fans are configured to operate based on a control signal. The system also can comprise a fan control logic board, wherein the fan control logic board is configured to receive from each node in the plurality of chassis the air flow requirements and based on the plurality of air flow requirements generate and transmit the control signal to the plurality of fans.

Optimized and intelligent fan control mechanism inside rack system

A system for sharing input/output using universal sleds includes a first universal sled that includes a first switch and a first universal node, and a second universal sled that includes a second switch and a second universal node, where the first universal sled and second universal sled have interchangeable physical dimensions. The midplane board includes a management processor and a midplane switch. The system further includes an input/output sled and a bus that connects the first universal sled, the second universal sled, the midplane board, and the input/output sled.

Universal sleds server architecture

Systems, methods, and computer-readable storage media for hardware recovery are disclosed. In some examples, a system can detect a hardware error and identify a system component associated with the hardware error. The system can then generate a request configured to trigger an operating system of the system to place the system in a particular operating state. The particular operating state can be determined based on a component type of the system component. The particular operating state can be a first sleep state when the component type is a peripheral component or a second sleep state when the component type is a processor, a memory, or a power supply. The second sleep state can result in a lower power resource consumption than the first sleep state. The system can generate an indication that the system component can be replaced without restarting the operating system.

Hardware recovery systems

Embodiments generally relate to a universal debug design which involves integrating a debug controller and a debug card with display together into a single debug design. Debug codes, such as power-on self-test (POST) codes and other error codes, are generated by various subsystems of a server-related system. The codes are transmitted to a controller, which stores the codes in memory. In some embodiments, a multiplexer outputs one debug code from the multitude of received codes, based on a user or event selecting which desired debug code should be displayed. In some embodiments, a decoder converts and sends the LED display signals to a debug card, which displays the debug code on a 7-segment LED display.

Universal debug design

A device, such as a baseboard management controller, monitors a physical-layer device in a server and at least one network connector/cable connected to the physical-layer device, determines a status of the physical-layer device or a status of the at least one network connector/cable indicates at least one of a warning or a failure, and transmits an alert corresponding to the at least one of the warning or the failure to a rack management controller.

Diagnostic monitoring techniques for server systems

A component carrier with a housing and a converter board disposed within the housing. The converter board including a U.2 connector, an M.2 connector configured to receive an M.2 solid state drive having a cache memory, and a capacitor. The capacitor provides backup power for a power loss protection system allowing flush cache storage. The housing configured to receive one or more M.2 solid state drives coupled with the converter board.

Component carrier with converter board

A method for automatic clock configurations is performed by a system having a host and a peripheral device. The host indicates on a first general-purpose input/output (GPIO) of a peripheral interface connecting the host and the peripheral device, whether the host supports a first clock configuration. The peripheral device receives from the first GPIO whether the host supports the first clock configuration. The peripheral device selects, in response to the host supporting the first clock configuration, use of a local clock of the peripheral device. The peripheral device selects, in response to the host not supporting the first clock configuration, use of a common clock of the host.

Automatic clock configuration system

A controller in a server system can determine whether to share a network connection of the server system. In response to determining to share the network connection, the controller can disable a dedicated network connection between the controller and a network interface controller (NIC) in the server system, enable a first shared network connection between the controller and a computing module in the server system, and enable a second shared network connection between the computing module and the NIC. In response to determining not to share the network connection, the controller can enable the dedicated network connection between the controller and the NIC.

Managing network configurations in a server system

Embodiments generally relate to thermal management in a multi-node computing device. The present technology discloses techniques that can receive multiple control signals from multiple computing nodes, each of the control signals being associated with a fan duty request, which is a request for a fan duty needed to keep a related computing node operating within a predetermined temperature range. The logic controller can rank the received control signals and select a control signal that requests a highest fan duty; lastly, the logic controller can cause multiple cooling fans to operate at the selected highest fan duty.

Fan duty control for multi-node computing device

A server cluster including a network switch and multiple server nodes is provided. The network switch is connected to an external network. Each server node performs an operation system and respectively includes a network port, a network chip and a south bridge chip. The network port is connected to the network switch via a cable. The network chip outputs a power-off signal according to a received power-off packet after the network switch is started. The south bridge chip outputs a shutdown signal to shut down the server node according to the power-off signal when the server node is turned on and the operation system is working normally.

Growing community of inventors

Taoyuan, Taiwan

Le-Sheng Chou