Globespan Virata Corporation

Globepan, Inc.

Lazslo Arato

Daniel Amrany

William J Santulli

A system and method to perform partial byte writes in a processor circuit is disclosed. The system comprises a bit assembly circuit having a bit assembly register with a corresponding shadow register. Also included is a bit routing circuit configured to transfer at least one data bit from a data bus to a predetermined register position in the bit assembly register and a shadow bit from the data bus to a corresponding register position in the shadow register. The shadow bit indicates that the data bit written comprises valid data. The bit assembly and shadow registers may receive data directly from the data bus as well. Using this circuitry, a partial parallel data block is assembled in the bit assembly register. Thereafter, the partial parallel data block is transferred to a destination register via the data bus with corresponding shadow bits being transmitted to the destination shadow register. The valid data is processed accordingly.

Circuit and method for performing partial parallel data transfer in a communications system

A physical interface unit and method are disclosed which are configured to receive a data stream which may use any one of a number of data communications protocols, and to transmit the same data stream using another one of the same number of data communications protocols. The physical interface unit is advantageously designed to operate in conjunction with a processor circuit to translate a data stream from a first data protocol to a second data protocol. The physical interface unit includes a first serial interface, a first asynchronous transfer mode (ATM) interface, and a first parallel interface. The physical interface also includes a second serial interface, a second ATM interface, and a second parallel interface. The first serial, ATM, and parallel interfaces are electrically coupled to a first FIFO circuit which interfaces with the processor circuit. Likewise, the second serial, ATM, and parallel interfaces are electrically coupled to a second FIFO circuit which interfaces with the processor circuit. One of the first serial, ATM, and parallel interfaces and one of the second serial, ATM, and parallel interfaces are enabled by a selection circuit. A bi-directional data stream using a first protocol is received from and transmitted to a first data endpoint by the enabled first interface and provided to the processor circuit for protocol translation. The same data stream is transmitted to and received from a second data endpoint from the processor circuit via the enabled second interface.

Multiple protocol interface and method for use in a communications system

The present invention entails a programmable data communications protocol conversion unit (PCU) and method. The PCU is a processor circuit which includes a means for performing full parallel, partial parallel, and bit data transfers. In particular, a bit assembly register is employed to assemble partial parallel data blocks which comprise data with a number of bits that is less than the order of the data bus of the PCU. The bit assembly register further includes the capability of writing the partial parallel data block to predetermined locations using a full parallel transfer and a shadow bus with bits indicating the validity of the particular bits in the data block transferred. The particular circuits receiving partial parallel writes include a register for receiving data and a register for receiving the corresponding shadow bits. Invalid data written to these registers is ignored while valid data is shifted accordingly, for example, out to a serial interface. The PCU further includes a task specific circuit for performing bit alignment and other tasks and a task specific circuit for generating cyclic redundancy check (CRC) data. The later circuit can create CRC data for any number of protocols as the circuit is highly configurable with a bit shift register of varying lengths.

System and method for protocol conversion in a communications system

A circuit and method for generating cyclic redundancy check (CRC) data is disclosed. In one embodiment, the circuit interfaces with a data bus with other processor components. The circuit includes an input first-in-first-out (FIFO) to interface with the data bus, a configuration register electrically coupled to the data bus, and a configurable CRC generation circuit electrically coupled to the data bus and to the configuration register. The CRC generation circuit includes a bit shift register which is configurable to generate CRC data for multiple protocols. To accomplish this, the bit shift register is configurable for different lengths, the actual length of the bit shift register being determined by the data communication protocols employed.

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Tinton Falls, NJ, United States of America

Lazslo Arato