Qualcomm Incorporated

Applied Micro Circuits Corporation

Silanna Asia Pte Ltd

Laxminarayan Sharma

Stuart B Molin

Mario Francisco Velez

Hong Yang

Siamak Fazelpour

Henry Laurel Sanchez

Hen Sanchez

Henry Sanchez

Conductive clip connection arrangements for semiconductor packages are disclosed. Some examples provide electrically conductive clip connection arrangements for semiconductor packages that improve electrical performance and fabrication reliability while maintaining compatibility with existing quality control processes. Some examples provide innovative conductive clip structures and die pad arrangements that broaden the range of options available for tailoring the physical configurations of one or more of the constituent conductive clips and/or die pads to achieve specific electrical performance targets.

Conductive clip connection arrangements for semiconductor packages

Die stacking systems and methods are disclosed. In an embodiment, a semiconductor device includes a passivation surface and a conductive die receiving surface located in an opening of the passivation surface. The conductive die receiving surface has a surface area that is larger than a footprint of a second die that is electrically coupled to the conductive die receiving surface.

Die stacking system and method

Die stacking systems and methods are disclosed. In an embodiment, a die has a surface that includes a passivation area, at least one conductive bond pad area, and a conductive stacked die receiving area sized to receive at least a second die.

The disclosure provides integrated circuit packages including a lead frame having multiple I/O pads positioned proximate to the lead frame perimeter around a central ground paddle, an integrated circuit die having electrically conductive die terminals positioned on the central ground paddle, and multiple ground circuit pads positioned on and in electrical connection with the central ground paddle. Electrically conductive I/O circuit pads are arranged about the die between the ground circuit pads and the I/O pads, each I/O circuit pad electrically connected to one of the I/O pads. Electrically conductive bond wires connect one or more of the die terminals to one or more I/O circuit pads or one or more ground circuit pads. In certain embodiments, the disclosure further provides an integrated circuit positioned to engage the integrated circuit die in electrical connection with the die terminals. The disclosure also relates to methods of packaging an integrated circuit to reduce packaging parasitics.

Integrated circuit packaging

A system and method have been provided for removing high lead content solder balls from the surface of a circuit package for the purpose of rework. The invention is applicable to ball grid array (BGA), C balls, chip scale balls, and flip chip bumps. Advantageously, the room temperature solder ball rework procedure minimizes damage to the circuit package. Specifically, a thin-film stainless steel mask with openings to expose the solder balls, is formed over the circuit package, and the solder balls are removed in a shearing or grinding operation, leaving a solder ball residue. Then, a conventional thick mask film is formed and a solder paste is deposited to fill the apertures. The solder ball residue forms a wettable surface for the low temperature attachment of new solder balls.

System and method for solder ball rework

An electronic device package includes a modified ball grid array (&ldquo;BGA&rdquo;) interconnect substrate upon which a flip-chip device is mounted. The flip-chip device includes one or more high speed input/output solder bumps corresponding to input/output signals having data rates of up to 40 Gbps. A high speed solder bump is directly connected to an interconnect via formed within the BGA substrate, and the via is directly connected to a respective BGA solder ball positioned at an interior point of the BGA solder ball matrix. The BGA substrate is void of BGA solder balls between the designated high speed BGA solder ball and at least one edge of the substrate, thus providing a clear path to the designated high speed BGA solder ball for a high speed conductive trace formed on a printed circuit board.

Growing community of inventors

San Diego, CA, United States of America

Laxminarayan Sharma