Chrontel Inc.

Lawrence Tze-Leung Tse

King Cheung Yen

Timothy J Donovan

Tat C Choi

David C Soo

Randy Pl Tsang

A high speed analog color key detection system is disclosed for video/graphics mixing that employs a high speed analog strobe comparator to compare the analog version of a pre-defined color key value to the stream of pixel values in an incoming analog graphics signal. When the comparator indicates a match, the display signal is switched from the analog graphics signal to an incoming analog video signal, enabling the analog video signal to be displayed within a graphics window. Comparisons are triggered by active transitions of a strobe signal with a frequency that is an integer k multiple of the frequency at which the pixel values are generated by a graphics card. Oversampling strobe signals (where the integer k is greater than one) enable comparisons to be performed on small segments of fat pixel values. The strobe signal is generated using a phase locked loop that is synchronized with a horizontal synchronization signal provided by the graphics card. The PLL also regenerates the pixel clock using the horizontal synchronization signal.

High speed analog color key detection technique and system

A clock-referenced switching bias current source is disclosed wherein an accurate bias current is established based on the charge dissipated by a switching capacitor over a predetermined period. The time period is established by a very accurate system clock. The value of the capacitor can be accurately selected with .+-.10%. By selecting a particular capacitance and frequency, a desired average bias current value is determined according to the amount of charge dissipated over the predetermined period. In different embodiments, the bias current source can be configured to provide a bandgap current that is temperature and/or process independent.

Clock-referenced switching bias current generator

An active pixel sensor implemented with CMOS technology that employs a plurality of photocells, each including a photodiode to sense illumination and a separate storage node with a stored charge that is discharged during an integration period by the photocurrent generated by the photodiode. Each photocell includes a switching network that couples the photocurrent to the storage node only during the integration period while ensuring that a relatively constant voltage is maintained across the photodiode during integration and non-integration periods. The transistors in the switching network operate in a forward active subthreshold region, ensuring linear operation and the diode voltage is clamped to a small positive voltage so that the diode is always reverse-biased. A source-follower generates a output signal correlated to the charge on the storage node that is coupled to column output circuitry that samples the signal. An operational scheme is employed wherein the storage node is first set to a defined voltage, the photocurrent is allowed to discharge the storage node and then the remaining charge coupled as a first signal to the column output circuitry, which samples and stores the first signal. The storage node is then reset to the same defined voltage and the resulting charge on the storage node is coupled as a second signal to the column output circuitry. The column output circuitry computes the difference of the first and second signals, which provides a reliable measure of the photocurrent during the integration period.

Active pixel sensor using CMOS technology with reverse biased photodiodes

A color space converter is implemented using current mode analog circuitry to efficiently transform video data from a YC.sub.b C.sub.r format to an RGB format in order to allow the display of video signals on a color monitor. The analog current-mode circuitry is implemented in an integrated circuit that will operate at high clock rates and can be integrated in a small die area so as to reduce its cost. The color space converter includes Y, C.sub.b and C.sub.r current-mode conversion circuits to compute Y, C.sub.b and C.sub.r contributions to the G, R and B signals, and current-mode adders that add those contributions to the G, R and B signals to generate the G, R and B signals. Each conversion circuit includes (A) a respective folded cascode structure having an input coupled to a respective analog Y, C.sub.b or C.sub.r signal, each conversion circuit generating a respective Y, C.sub.b or C.sub.r current output; (B) at least one respective current mirror that generates from the Y, C.sub.b or C.sub.r current output an unadjusted Y, C.sub.b or C.sub.r contribution to at least one of the G, R and B signals, and (C) at least one current adder for subtracting respective offset currents from the unadjusted Y, C.sub.b or C.sub.r contribution to at least one of the G, R and B signals to provide the Y, C.sub.b or C.sub.r contribution to at least one of the G, R and B signals.

Fast current-mode analog circuit for converting video data signals

A RAMDAC circuit drives a display device so as display multiple modes of color depth and display resolution in a single display frame without sacrificing resolution of the higher-resolution mode, and adjusts the output pixel rate to match that of the display mode being display on a pixel-by-pixel basis. The RAMDAC circuit switches between two graphics modes on-the-fly on a pixel-by-pixel basis in accordance with mode control bits stored in the pixel data. Furthermore, the RAMDAC circuit switches between two output pixel rates such that the amount of video memory used for any predefined screen area remains constant even though the output pixel rate and resolution are dynamically adjusted. In a preferred embodiment a display mode signal is embedded in the display data such that the display data, including the mode signal, comprises one byte of data for each display pixel when the mode signal specifies the first display mode, and comprises two bytes of data for each display pixel when the mode signal specifies the second display mode.

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San Jose, CA, United States of America

Lawrence Tze-Leung Tse