Intel Corporation

Arizona State University

Mie Fujitsu Semiconductor Limited

Marvell International Limited

Suvolta, Inc.

Arizona Board of Regents, a Body Corporate

Stc.unm

Intle Corporation

Lawrence T Clark

Scott E Thompson

Eric J Hoffman

Richard Stephen Roy

Mark A Beiley

David Anthony Kidd

Michael W Morrow

Robert Rogenmoser

Dan Wheeler Patterson

Dennis M O'Connor

Samuel Leshner

Augustine Kuo

Jay B Miller

Edward John Bawolek

Damodar Reddy Thummalapally

Bart R McDaniel

David R Allee

Jay S Heeb

Franco Ricci

Tuan X Do

Vikas R Amrelia

Raphael A Soetan

Srivatsan Chellappa

Zane A Ball

Aviram Gutman

Kimberley E Wagner

Satendra Kumar Maurya

Neil F Deutscher

Thomas J Mozdzen

Sameer M Venugopal

Chao-Wu Chen

Mark A Schaecher

Gregory B Tucker

Richard J Burgess, Jr

Nathan D Hindman

Michael S McGregor

Shay P Demmons

Tom J Adelmeyer

Giby Samson

Xiaoyin Yao

Karl C Mohr

Keith E Holbert

Chandarasekaran Ramamurthy

George Tien

Yuan-Po Ypt Tseng

Ali Minaei

Lucian Shifren

Derek L Davis

Gregory F Taylor

Timothy J Maloney

James Adams

Stephen J Strazdus

Jean-Charles Korta

Terry L Alford

Bruce Marshall McWilliams

Timothy S Beatty

David E Pettit

Robert D Bateman

Manish Biyani

Constantine A Balanis

Rahul Shringarpure

James T Aberle

Adam Brand

William J Spaw

Yu Cao

Nazanin Darbanian

Matthew M Clark

Pradeep Elamanchili

Tim Beatty

Sushil Kumar

Kevin Baugh

Vinay Vashishtha

E J N Tsangaris

Aditya Gujja

Siddhesh Mhambrey

Sayeed Ahmed Badrudduza

Jonathan E Knudsen

John K McIver, Iii

Kyle E Nielsen

Susan M Graham

Dale J Brown

Sandeep Shambhulingaiah

Neil F Duetscher

Systems and methods for multi-mode radiation hardened multi-core microprocessors are disclosed. In some embodiments, a triplicated circuit includes a first core logic, a second core logic, a third core logic, and bus arbitration and control circuitry. The triplicated circuit is configurable to operate in both a Triple-Modular Redundant (TMR) mode of operation and a multi-threaded mode of operation. In some embodiments, there is essentially no overhead in soft mode and low overhead (power only) in hard mode. In most applications, it is expected that portions of missions require very hard systems (e.g., landing) where a failure is catastrophic. However, other portions require essentially no hardening (digital signal processor and signal processing activities) but much better throughput. Consequently, there is a huge opportunity to develop computer processors with low overhead in soft mode and unprecedented hardness in hard mode.

Multi-mode radiation hardened multi-core microprocessors

Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.

Digital circuits having improved transistors, and methods therefor

This disclosure relates generally to physically unclonable function (PUF) circuitry along with methods of generating numbers. In one embodiment, the PUF circuitry includes a memory, a memory control circuitry, and whitening circuitry. To reduce or eliminate the systematic bias from the array, whitening circuitry is configured to generate a random number comprising random number bits in response to the memory control circuit implementing at least one sequence of memory cycles on the array of the memory cells in the memory. The whitening circuitry is configured to provide the random number bits of the random number based on the variable bit states stored by the array of the memory cells. On average the whitening circuitry is configured to provide approximately half of the random number bits in the first bit state and half of random number bits in a second bit state.

Secure true random number generation using 1.5-T transistor flash memory

An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple SRAM cells.

Integrated circuit devices and methods

A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.

Integrated circuit device body bias circuits and methods

Embodiments of an sequential state element (SSE) capable of providing triple modular redundant (TMR) correction is disclosed. The SSE has a setup stage and a feedback stage. The setup stage is configured to generate an output bit signal having an output bit state while a clock signal is in the first clock state. The setup stage also generates a feedback input bit signal as feedback of the output bit state. However, the feedback stage is capable of providing TMR correction without this feedback signal. Instead, the feedback stage utilizes the second feedback input bit signal and a third feedback input bit signal from two other SSEs. Since TMR correction can be provided with just the second feedback input bit signal and the third feedback input bit signal, the power and area consumed by the SSE is reduced.

Muller C-element as majority gate for self-correcting triple modular redundant logic with low-overhead modes

Instruction issue circuits are disclosed that are configured to issue multiple instructions within a superscalar pipeline of a microprocessor. The instruction issue circuit includes an instruction queue that stores instructions. A ready generation circuit is operably associated with the instruction queue and generates ready signals that indicate which instructions in the instruction queue are ready for execution. To simplify the instruction issue circuit, the instruction issue circuit has group blocks. Each group block receives a different group of the ready signals corresponding to a different group of the instructions. Each group block generates a group output indicating a group set within the corresponding group of the instructions that has a highest instruction execution priority and are ready for execution. By splitting the ready signals into groups, the groups of ready signals can be processed in parallel thereby reducing both the resulting delay and complexity of the instruction issue circuit.

Low complexity out-of-order issue logic using static circuits

This disclosure relates generally to computerized systems and methods of producing a physical representation of an in silico Integrated Circuit (IC) having an in silico Multi-Mode Redundant (MMR) pipeline circuit. An IC layout of the in silico IC is initially generated with the electronic design automation (EDA) program. Multi-Mode Redundant Self-Correcting Sequential State Element (MMRSCSSE) layouts are then rendered immotile while initial redundant Combinational Logic Circuit (CLC) layouts are removed from the IC layout after the MMRSCSSE layouts have been rendered immotile. By first placing the MMRSCSSE layouts and then rendering them immotile, the remaining logic can be placed again and optimized without compromising critical node spacing. As such, the described method provides for a more efficient way to create the IC layout of the in silico IC while maintaining critical node spacing.

Techniques for generating physical layouts of in silico multi mode integrated circuits

This disclosure relates generally to radiation hardened digital circuits. In one embodiment, a radiation hardened digital circuit includes a delay network and a first Muller C element. The delay network is configured to generate a first delayed clock signal from a global clock signal such that that the first delayed clock signal is delayed with respect to the global clock signal. The first Muller C element is configured to generate a first clock input signal and set the first clock input signal to one of a set of clock states in response to the first delayed clock signal and the global clock signal each being provided in a same one of the set of clock states and is configured to hold the first clock input signal otherwise. Thus, a radiation strike is prevented from causing a soft error in the first clock input signal.

Radiation hardened digital circuit

A dynamic random access memory (DRAM) can include at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor; a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being different from power supply voltages of the DRAM; and peripheral circuits formed in the same substrate as the at least one DRAM array, the peripheral circuits comprising deeply depleted channel (DDC) transistors having bodies coupled to receive the body bias voltage, each DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region.

Dynamic random access memory (DRAM) with low variation transistor peripheral circuits

Growing community of inventors

Phoenix, AZ, United States of America

Lawrence T Clark