Intel Corporation

Lawrence Smith, Iii

Gilbert A Neiger

Andrew V Anderson

Steven M Bennett

Scott Dion Rodgers

Richard A Uhlig

Rajesh Sankaran Madukkarumukumana

Richard UhligQ

Barry E Huntley

Xiang Chris Zou

Stalinselvaraj Jeyasingh

Alain Kagi

A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

Virtualizing physical memory in a virtual machine system using a hierarchy of extended page tables to translate guest-physical addresses to host-physical addresses

In one embodiment, a predefined behavior of a virtual machine monitor (VMM) with respect to one or more virtual machines (VMs) is identified, and processor-managed resources associated with the one or more VMs are utilized based on the predefined behavior of the VMM.

Optimizing processor-managed resources based on the behavior of a virtual machine monitor

Using permission bits in translating guests virtual addresses to guest physical addresses to host physical addresses

Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and evaluation logic. The event logic is to recognize a virtualization event. The evaluation logic is to determine whether to transfer control from a child guest to a parent guest in response to the virtualization event.

Virtualization event processing in a layered virtualization architecture

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Beaverton, OR, United States of America

Lawrence Smith, Iii