International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Lawrence Shungwei Mok

Thomas Mario Cipolla

Daniel Peter Morris

Paul William Coteus

Evan G Colgan

Minhua Lu

Alphonso Philip Lanzetta

George L Chiu

Gareth Geoffrey Hougham

Vinod Kamath

Richard Ian Kaufman

Paul Stephen Andry

Alan G Gara

Todd Edward Takken

Matthias Augustin Blumrich

David Andrew Lewis

Howard Hao Chen

Chirag Suryakant Patel

David Earle Seeger

Gerard Vincent Kopcsay

Trieu Can Chieu

Ephraim Bemis Flint

Paul F Greier

Robert K Montoye

Philip Heidelberger

Sri Muthuthamby Sri-Jayantha

Da-Yuan Shih

Chandrasekhar Narayan

Louis C Hsu

Mark Edwin Giampapa

Sung Kwon Kang

Hien Phu Dang

Arun Sharma

Leathen Shi

Ho-Ming Tong

Raymond R Horton

Dong Chen Chen

Kei-Hsiung Yang

Hoi Yeung Chan

Glen Walden Johnson

Robert Lee Melcher

Linda C Matthew

Thomas Y Kwok

Tsorng-Dih Yuan

Mohanlal Savji Mansuria

J Campbell Scott

Peter G Ledermann

Joseph Maryan Milewski

Robert E Schwall

Hussain Shaukatulla

Tarek J Jamal-Eddine

Clifford A Pickover

Louis L Hsu

Dong Chen

Paul Andrew Moskowitz

Tin-Lup Wong

Brian Paul Gaucher

Albert Vincent Makley

Joseph Anthony Holung

Fusanobu Nakamura

Michael J Palmer

Hiroaki Agata

Michael Philip Goldowsky

Stanley Joseph Whitehair

Michael Frank Cina

Ismail C Noyan

Modest M Oprysko

Brenda Lynn Dietrich

Gaetano Paolo Messina

Robert Stephen Olyha, Jr

Harry R Bickford

Santhosh Babu Kumaran

Hsichang Liu

David Leslie Cohn

Saila Ponnapalli

Stephen Dale Linam

Arthur Wood Ellis

William Edward Pence, Iv

Roger Alan Pollak

Leo Harold Webster, Jr

M Lawrence Buller

George Liang-Tai Chiu

Ricky A Rand

Thomas Richard Hildner

Fumitoshi Kiyooka

Arthur Robert Williams

John J Liutkus

Shiwa S Fu

Peter H Bruhn

Frank J Canora

Christina M Knoedler

Mark John Allen

Barbara J McNelis

Brian D Arldt

Manish Bahl

Pablo D Quinones

Jeffrey Joseph Kleikamp

Mark E Giampap

Brian C Derdall

Philip Heidlberger

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. The multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions.

Massively parallel supercomputer

A method and system of predicting a maintenance schedule and estimating a cost for warranty service of systems, for example, hardware systems, is provided. The method and system in one aspect may collect component usage data and obtain component reliability data for each of the plurality of components. A component life distribution module (CLDM) may be constructed based on the real time component usage data and the component reliability data, and from CLDM a mean time to fail data may be obtained. A system life distribution model (SLDM) may be selected and the mean time to fail data input into the SLDM to obtain an operating environment index that represents the effect of environment conditions on the lifetime and reliability. A maintenance schedule may be predicted and an adjusted cost of warranty service may be calculated based on the operating environment index for each of the plurality of components.

System to improve predictive maintenance and warranty cost/price estimation

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System- On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. The multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions.

An arrangement for improving the cooling efficiency of semiconductor chips. One embodiment is to construct a vapor chamber with one compliant surface for improving the efficiency of transferring heat from a semiconductor chip to the vapor chamber, and another embodiment is to construct a vapor chamber with the chip substrate such that the chips are embedded inside the vapor chamber. One surface of the vapor chamber has a flexible structure to enable the surface of the vapor chamber to be compliant with the surface of a chip or a heat sink device.

Compliant vapor chamber chip packaging

A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously.

Laser annealing for 3-D chip integration

A structure. The structure includes an interposer adapted to be interposed between a heat source and a heat sink and to transfer heat from the heat source to the heat sink. The interposer includes an enclosure that encloses a cavity. The enclosure is made of a thermally conductive material. The cavity includes a thermally conductive foam material. The foam material includes pores and includes at least one serpentine channel. Each serpentine channel has at least two contiguously connected channel segments. Each serpentine channel independently forms a closed loop or an open ended loop. The foam material is adapted to be soaked by a liquid filling the pores. Each serpentine channel is adapted to be partially filled with a fluid that serves to transfer heat from the heat source to the heat sink.

Cooling of substrate using interposer channels

A method of forming a structure. An interposer is provided. The interposer is adapted to be interposed between a heat source and a heat sink and to transfer heat from the heat source to the heat sink. The interposer includes an enclosure that encloses a cavity. The enclosure is made of a thermally conductive material. The cavity includes a thermally conductive foam material. The foam material includes pores and includes at least one serpentine channel. Each serpentine channel has at least two contiguously connected channel segments. Each serpentine channel independently forms a closed loop or an open ended loop. The foam material is adapted to be soaked by a liquid filling the pores. Each serpentine channel is adapted to be partially filled with a fluid that serves to transfer heat from the heat source to the heat sink.

Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.

Integrated circuit chip module with microchannel cooling device having specific fluid channel arrangement

A portable computer adapted for electrical connection to a docking station having multiple power modes of operation is described. The portable computer has one or more CPU chips which have at least two power modes of operation, a low power mode and a high power mode. When the portable computer is operated as a stand-alone computer, it operates in the low power mode. When the portable computer is operated while electrically connected to the docking station, it operates in a high power mode. The docking station has greater cooling capacity than the portable computer alone to provide enhanced cooling of the high power mode of operation.

Method of fabricating a portable computer apparatus with thermal enhancements and multiple power modes of operation

A structure. The structure includes a substrate and an interposer. The substrate includes a heat source and N continuous substrate channels on a first side of the substrate (N&#x2267;2). The interposer includes N continuous interposer channels coupled to the N substrate channels to form M continuous loops (1&#x2266;M&#x2266;N). Each loop independently consists of K substrate channels and K interposer channels in an alternating sequence. For each loop, K is at least 1 and is subject to an upper limit consistent with a constraint of the M loops collectively consisting of the N interposer channels and the N substrate channels. Each loop is independently open ended or closed. The first side of the substrate is connected to the interposer. The interposer is adapted to be thermally coupled to a heat sink such that the interposer is interposed between the substrate and the heat sink.

Electronic module comprising memory and integrated circuit processor chips formed on a microchannel cooling device

A method of forming structure. A substrate and an interposer are provided. The substrate includes a heat source and N continuous substrate channels on a first side of the substrate (N&#x2267;2). N interposer channels are coupled to the N substrate channels so as to form M continuous loops (1&#x2266;M&#x2266;N). Each loop independently consists of K substrate channels and K interposer channels in an alternating sequence. For each loop, K is at least 1 and is subject to an upper limit consistent with a constraint of the M loops collectively consisting of the N interposer channels and the N substrate channels. Each loop is independently open ended or closed. The first side of the substrate is connected to the interposer. The interposer is adapted to be thermally coupled to a heat sink such that the interposer is interposed between the substrate and the heat sink.

Method of forming a substrate with interposer channels for cooling the substrate

A method, system and computer readable medium for maximizing the performance of a computer system that includes at least one computing unit. Temperature and location data for each computing unit is received by a server unit and the location of each computing unit within a given environment is reevaluated and revised to maximize the overall performance of the computer system.

Computer system performance estimator and layout configurator

A microelectronic device is made of a semiconductor substrate, a heat generating component in a layer thereof, and a body within the remaining semiconductor substrate. The body is made of materials which have a high thermal inertia and/or thermal conductivity. When high thermal conductivity materials are used, the body acts to transfer the heat away from the substrate to a heat sink.

Microelectronic devices and methods

Growing community of inventors

Brewster, NY, United States of America

Lawrence Shungwei Mok