Freescale Semiconductor,inc.

Motorola Corporation

Nxp Usa, Inc.

Lawrence Scott Klingbeil

Bruce McRae Green

Charles E Weitzel

Olin L Hartin

Ellen Y Lan

Randy D Redd

Hsin-Hua P Li

Leo M Higgins, Iii

Bernhard Grote

Darrell Glenn Hill

Trent Uehling

Brett P Wilkerson

Karen Elizabeth Moore

James Allen Teplik

Colby Greg Rampley

Yuanzheng Yue

George C Chen

Fred Reece Clayton

Congyong Zhu

Anthony Ciancio

Jenn-Hwa Huang

Paul A Fisher

Mostafa Vadipour

Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a gate electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers.

Transistors with source-connected field plates

A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with a contact region formed within the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.

Semiconductor device with selectively etched surface passivation

A method forms a connecting pillar to a bonding pad of an integrated circuit. A seed layer is formed over the bond pad. Photoresist is deposited over the integrated circuit. An opening is formed in the photoresist over the bond pad. The connecting pillar is formed in the opening by plating.

Semiconductor devices with compliant interconnects

A method and system for uniquely identifying each semiconductor device die from a wafer is provided. Identifying features are associated with device die bond pads. In one embodiment, one or more tab features are patterned and associated with each of one or more device die bond pads. These features can represent a code (e.g., binary or ternary) that uniquely identifies each device die on the wafer. Each tab feature can be the same shape or different shapes, depending upon the nature of coding desired. Alternatively, portions of the one or more device die bond pads can be omitted as a mechanism for providing coded information, rather than adding portions to the device die bond pads.

Identification mechanism for semiconductor device die

In one embodiment of the invention, a semiconductor component includes a semiconductor substrate (), a first dielectric layer () above the semiconductor substrate, a first ohmic contact region () and a second ohmic contact region () above the semiconductor substrate, a gate electrode () above the semiconductor substrate and between the first ohmic contact region and the second ohmic contact region, a field plate () above the first dielectric layer and between the gate electrode and the second ohmic contact region, a second dielectric layer () above the field plate, the first dielectric layer, the first ohmic contact region, and the second ohmic contact region, and a third dielectric layer () between the gate electrode and the field plate and not located above the gate electrode or the field plate.

Method of manufacturing a semiconductor component that includes self-aligning a gate electrode to a field plate

A microwave field effect transistor () has a high conductivity gate () overlying a double heterojunction structure () that has an undoped channel layer (). The heterojunction structure overlies a substrate (). A recess layer that is a not intentionally doped (NID) layer () overlies the heterojunction structure and is formed with a predetermined thickness that minimizes impact ionization effects at an interface of a drain contact of source/drain ohmic contacts () and permits significantly higher voltage operation than previous step gate transistors. Another recess layer () is used to define a gate dimension. A Schottky gate opening () is formed within a step gate opening () to create a step gate structure. A channel layer () material of InGaAs is used to provide a region of electron confinement with improved transport characteristics that result in higher frequency of operation, higher power density and improved power-added efficiency.

Method for forming a microwave field effect transistor with high operating voltage

A method for patterning a substrate having a surface with high aspect ratio topography with a photoresist is described. Specifically the surface of a semiconductor substrate is pre-wetted with a solvent solution to form a liquid solvent film. An additional amount of the solvent solution is added to form a solvent puddle on the liquid solvent film. Photoresist is dispensed onto the solvent puddle for a sufficient time and in a sufficient amount to allow diffusion of the photoresist and the solvent puddle into the openings defined in the topography of the substrate. The solvent solution in and on the surface of the openings defined in the substrate from the pre-wetting step is replaced with the photoresist by facilitating diffusion of the photoresist into the topography openings. A photoresist layer is then cast in a predetermined thickness on the surface of the substrate.

Method for patterning a substrate with photoresist

A method of manufacturing a semiconductor device includes providing an apparatus (210, 510) having tabs (212, 214, 412, 414) for holding and separating semiconductor substrates wherein a first tab (212, 412) is different from a second tab (214, 414), using the first tab (212, 412) to support a semiconductor substrate (224) wherein the second tab (214, 414) does not support the semiconductor substrate (224), and exposing the semiconductor substrate (224) to a chemical to move the semiconductor substrate (224) towards the second tab (214, 414) without removing the semiconductor substrate (224) from the apparatus (210, 510).

Method of manufacturing a semiconductor device and apparatus therefor

Growing community of inventors

Chandler, AZ, United States of America

Lawrence Scott Klingbeil