Acacia Communications, Inc.

Lawrence S Pellach

Eric A Swanson

Graeme Pendock

Edward H Truex

Bhupendra Shah

Bhupen Shah

Methods and apparatus for controlling the power-on current transients and for providing a gradual current draw in an ASIC or FPGA having a high gate count and a number of physical blocks are disclosed. Additionally, method(s) are disclosed which ensure related blocks emerge from a reset state on a common clock cycle even when the related blocks are geographically dispersed over a large area producing multiple clock cycle latency periods for signals between blocks. Complete flexibility of physical block start up is achieved by software control which permits the sequence and number of physical blocks started simultaneously.

Staggered power-up and synchronized reset for a large ASIC or FPGA

A method for setting transceiver transmission parameters, in a transceiver having a plurality of components, to achieve the predetermined acceptable end-to-end bit error rate while reducing power consumption. In another aspect the invention relates to an optical transceiver system that uses digital signal processing to process the data stream sent through a fiber optical channel to compensate for transmission, reception and channel impairments to achieve the a predetermined end-to-end bit error rate and to alter its power dissipation to that sufficient to meet said end-to-end bit error rate. In one embodiment the optical transceiver system includes an optical transmitter; an optical receiver comprising an ASIC, FPGA, or other circuitry; and a controller in electrical communication with the optical receiver, wherein the controller controls power to portions of the ASIC so as to reduce power dissipation while meeting the end-to-end bit error rate.

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Malden, MA, United States of America

Lawrence S Pellach