Synopsys, Inc.

Lawrence S Melvin, Iii

Qiliang Yan

Jensheng Huang

James Patrick Shiely

Chun-Chieh Kuo

Benjamin David Painter

Jianliang Li

Yudhishthir Prasad Kandel

Artak Isoyan

Weiping Fang

Hua Song

Levi D Barnes

Daniel Zhang

Juhwan Kim

Zong Wu Tang

Frank L Ferschweiler

Ulrich Karl Klostermann

Kunal N Taravade

Kevin Hooker

Daniel F Beale

Martin Drapeau

William Stanton

Sylvain Berthiaume

Brian S Ward

Qilang Yan

Abani M Biswas

Alakananda A Biswas, Legal Representative

Ebo Kg Croffie

Ulrich Klostermann

Charlie Chung-ping Chen

The independent claims of this patent signify a concise description of embodiments. Roughly described, a design team prioritizes polygons of a circuit design layout. This information is then encoded into a layout database that is passed to the manufacturing team for correction further processing toward tape-out. The priorities may be used by an engineer to disposition errors found in the layout. For example, a failure may be waived. In another embodiment, the priorities are used during hotspot fixing, a process where failed features are corrected. In hotspot fixing, the priority can be used to make correction tradeoffs in favor of the highest priority features. Priorities are set during the correction to favor fidelity of the higher priority features over the lower priority features. Each embodiment reduces cost, and in some cases, improve final device performance. This Abstract is not intended to limit the scope of the claims.

Prioritized mask correction

A lithography process is described by a design for a lithographic mask and a description of the lithography configuration, which may include the lithography source, collection/illumination optics, projection optics, resist, and/or subsequent fabrication steps. The actual lithography process uses a lithographic mask fabricated from the mask design, which may be different than the nominal mask design. A mask fabrication model models the process for fabricating the lithographic mask from the mask design. Typically, this is an electron-beam (e-beam) process, which includes e-beam exposure of resist on a mask blank, processing of the exposed resist to form patterned resist, and etching of the mask blank with the patterned resist. The mask fabrication model, usually in conjunction with other process models, is used to estimate a result of the lithography process. Mask correction is then applied to the mask design based on the simulation result.

Using mask fabrication models in correction of lithographic masks

A method of generating a mask used in fabrication of a semiconductor device includes, in part, selecting a source candidate, generating a process simulation model that includes a stochastic variance band model in response to the selected source candidate, performing a first optical proximity correction (OPC) on the data associated with the mask in response to the process simulation model, assessing one or more lithographic evaluation metrics in response to the OPC mask data, computing a cost in response to the assessed one or more lithographic evaluation metrics, and determining whether the computed cost satisfies a threshold condition. In response to the determination that the computed cost does not satisfy the threshold condition, a different source candidate may be selected.

Inclusion of stochastic behavior in source mask optimization

A method, includes, in part, defining a continuous signal, defining a threshold value, calibrating the continuous signal and the threshold value from measurements made on edges of one or more patterns on a mask and corresponding edges of the patterns on a wafer, convolving the continuous signal with a kernel to form a corrected signal, and establishing, by a processor, a probability of forming an edge at a point along the corrected signal in accordance with a difference between the value of the corrected signal at the point and the calibrated threshold value. The kernel is calibrated using the same measurements made on the patterns' edges.

Stochastic signal prediction in compact modeling

An EUV mask absorber formed on a semiconductor structure, includes, in part a sidewall forming am angle relative to a surface of the semiconductor structure that is less than 90 degrees. The sidewall includes a layer of reflective material. The semiconductor structure may include, in part, a multitude of layers. The semiconductor structure may be disposed on a glass substrate, a silicon substrate, or the like. The EUV mask absorber is adapted to shift a phase of the EUV light passing therethrough. The EUV mask absorber may further include, in part, a layer of Ruthenium near a bottom surface of the absorber structure. The EUV mask absorber may further includes, in part, a layer of reflective material near a top surface of the absorber structure. The EUV mask absorber may further include, in part, Tantalum Oxynitride.

Undercut EUV absorber reflective contrast enhancement

Certain aspects relate to a method for improving a lithography configuration. In the lithography configuration, a source illuminates a mask to expose resist on a wafer. A processor determines a defect-based focus exposure window (FEW). The defect-based FEW is an area of depth of focus and exposure latitude for the lithography configuration with an acceptable level of defects on the wafer. The defect-based FEW is determined based on a predicted probability distribution for occurrence of defects on the wafer. A processor also determines a critical dimension (CD)-based FEW. The CD-based FEW is an area of depth of focus and exposure latitude for the lithography configuration with an acceptable level of CD variation on the wafer. It is determined based on predicted CDs on the wafer. The lithography configuration is modified based on increasing an area of overlap between the defect-based FEW and the CD-based FEW.

Lithography improvement based on defect probability distributions and critical dimension variations

Techniques and systems for improving wafer contrast by manipulating reflective extreme ultraviolet (EUV) mask absorber are described. Some embodiment disclosed herein provide for EUV absorber material, which transmits some EUV illumination, to suppress the printing of sub-resolution assist features (SRAFs) while making the SRAFs closer in size to the printed feature by thinning the SRAF absorber thickness from the nominal mask absorber thickness in the bright-field mask case. In the dark-field mask case, a layer of absorber material is left in the SRAF trenches to prevent SRAF printing.

Reflective EUV mask absorber manipulation to improve wafer contrast

Design-prioritized mask correction

A method of compensating for degradation of an optical source includes in part, generating a first model of the optical source at a first point in time, generating a second model of the optical source at a second point in time occurring after the first point in time, determining the difference between the first and second models, and varying a dose of the optical source if the determined difference is greater than a first threshold value. The compensation method optionally includes, in part, varying a focus distance of the optical source if the determined difference is greater than the first threshold value. The generation of the first model optionally includes, in part, generating wafer data from the optical source, and generating an optical proximity correction (OPC) model from the wafer data. The optical source may be an extreme ultraviolet optical source.

Optical source compensation

A photolithography model used in an optical proximity correction process modifies an image output intensity of a point disposed along a two dimensional plane and having coordinates (x,y) in accordance with a gradient of a convolution of a mask value at the point and a sampling pattern function selected at the point. The sampling pattern function includes, in part, a first subset of sampling patterns and a second subset of sampling patterns. The first subset of sampling patterns includes first and second nodes. The second subset of sampling patterns include first and second antinodes. The gradient of the convolution of the mask value and the first and second nodes of the first subset are scaled by a first coefficient. The gradient of the convolution of the mask value and the first and second antinodes of the second subset are scaled by a second coefficient.

Compact modeling for the negative tone development processes

A method, system or computer usable program product for building a fast lithography OPC model that predicts semiconductor manufacturing process outputs on silicon wafers including providing a first principles model of the semiconductor manufacturing process, providing a set of empirical data for storage in memory, utilizing a processor to develop a rigorous model for a process condition from the first principles model and the set of empirical data, and utilizing the processor running the rigorous model to generate emulated data for the process condition to develop a virtual model for predicting the semiconductor manufacturing process outputs.

Compact OPC model generation using virtual data

Systems and techniques for performing resolution enhancement on target patterns based on holographic imaging technique (HIT) are described. During operation, an electronic design automation (EDA) tool can compute an in-line hologram of the target patterns based on parameters associated with a photolithography process that is used in a semiconductor manufacturing process, wherein the semiconductor manufacturing process is to be used for printing the target patterns on a semiconductor wafer. Next, the EDA tool can determine the mask patterns based on the in-line hologram.

Resolution enhancement techniques based on holographic imaging technology

A lithography model uses a transfer function to map exposure energy dose to the thickness of remaining photoresist after development; while allowing the flexibility to account for other physical processes. In one approach, the model is generated by fitting empirical data. The model may be used in conjunction with an aerial image to obtain a three-dimensional profile of the remaining photoresist thickness after the development process. The lithography model is generally compact, yet capable of taking into account various physical processes associated with the photoresist exposure and/or development process for more accurate simulation.

Fast photolithography process simulation to predict remaining resist thickness

One embodiment of the present invention provides techniques and systems for determining modeling parameters for a photolithography process. During operation, the system can receive a layout. Next, the system can determine an iso-focal pattern in the layout. The system can then determine multiple aerial-image-intensity values in proximity to the iso-focal pattern by convolving the layout with multiple optical models, wherein the multiple optical models model the photolithography process's optical system under different focus conditions. Next, the system can determine a location in proximity to the iso-focal pattern where the aerial-image-intensity values are substantially insensitive to focus variations. The system can then use the location and the associated aerial-image-intensity values to determine an optical threshold and a resist bias. The optical threshold and the resist bias can then be used for modeling the photolithography process.

Method and apparatus for determining an optical threshold and a resist bias

One embodiment provides a system for determining a process model for a photolithography process. The photolithography process can use multiple exposure-and-development steps to create features on a wafer. When the photolithography process exposes the wafer to a layout, the wafer can include topography variations which were caused by previous exposure-and-development steps. The process model can be used to predict patterns that are created on the wafer when the wafer is exposed to a second layout, wherein the wafer includes topography variations that were caused by resist features that were created when the wafer was exposed to a first layout. The process model can include a first term and a second term, wherein the first term is convolved with a sum of the first layout and the second layout, and wherein the second term is convolved with the second layout.

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Hillsboro, OR, United States of America

Lawrence S Melvin, Iii