International Business Machines Corporation

Lawrence Robert Blumberg

Robert Maynard Japp

William John Rudik

John Frank Surowka

Mark David Poliks

Douglas Duane Coolbaugh

Kostas I Papathomas

Bernd Karl Appelt

John Joseph Konrad

William T Chen

Stephen Joseph Fuerniss

Timothy Leroy Wells

Richard Allen Day

Jeffrey McKeveny

Norman A Card

William Thomas Fotorny

Amarjit S Rai

Ross Downey Havens

Jan Obrzut

John A Kurowski

Eugene A Stromecki

A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. One embodiment of the reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The method for making reduced CTE laminate and laminate structures comprises the following steps: providing non-woven quartz mat; providing a prepreg, preferably B-stage cured to not more than about 40%, preferably not more than 30% of full cure; sandwiching the non-woven quartz mat between two layers of prepreg, and reflowing the resin of the prepreg into the quartz mat.

Method for reducing coefficient of thermal expansion in chip attach packages

A simple, inexpensive, drillable, reduced CTE laminate and circuitized structure comprising the reduced CTE laminate, is provided. The reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The present invention also generally relates to a method for reducing the CTE of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate. The method for making reduced CTE laminate and laminate structures comprises the following steps: providing non-woven quartz mat; providing a prepreg, preferably B-stage cured to not more than about 40%, preferably not more than 30% of full cure; sandwiching the non-woven quartz mat between two layers of prepreg, and reflowing the resin of the prepreg into the quartz mat. The method further comprises providing a resin volume percent, woven glass cloth volume percent and metal volume percent of the circuitized structure to be fabricated; selecting a desired CTE for the circuitized structure to be fabricated; and determining the amount of non-woven quartz or non-woven glass mat to be incorporated according to a formula. Optionally, the reduced CTE laminate is sandwiched between two layers of metal, preferably copper.

Through-holes in a substrate are masked during plating of the substrate by substantially filling the through-holes with a liquid material, followed by applying a photoimageable material to an external surface of the substrate, forming a predetermined pattern in the photoimageable material, circuitizing the predetermined pattern and then removing both the photoimageable material and the liquid material from the through-holes.

Method for masking a hole in a substrate during plating

A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. The reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The present invention also generally relates to a method for reducing the CTE of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate. The method for making reduced CTE laminate and laminate structures comprises the following steps: providing non-woven quartz mat; providing a prepreg, preferably not B-stage cured to not more than about 40%, preferably not more than 30% of full cure; sandwiching the non-woven quartz mat between two layers of prepreg, and reflowing the resin of the prepreg into the quartz mat. Optionally, the reduced CTE laminate is sandwiched between two layers of metal, preferably copper.

A fabric material and method of its manufacture suitable for use in electronic packages including chip carriers. High insulation resistance is exhibited when subjected to high temperatures and humidity stress conditions.

Laminate and method of manufacture thereof

A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. The reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The present invention also generally relates to a method for reducing the CTE of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate. The method for making reduced CTE laminate and laminate structures comprises the following steps: providing non-woven quartz mat; providing a prepreg, preferably B-stage cured to not more than about 40%, preferably not more than 30% of full cure; sandwiching the non-woven quartz mat between two layers of prepreg, and reflowing the resin of the prepreg into the quartz mat. Optionally, the reduced CTE laminate is sandwiched between two layers of metal, preferably copper.

Method for reducing coefficient of thermal expansion in chip attach

A method of minimizing forming of white spots and delamination of a copper plane bonded to one surface of a dielectric material following additive pattern plating of copper onto the other surface of the material and in vias contacting the copper plane utilizing a plating solution containing a reducing agent and the resulting product is provided. The surface of the copper which has been bonded to the one surface of the dielectric has been treated, preferably by a sodium chlorite treatment to form a chemical roughened surface of copper oxide (CuO and CuO(II)) on the copper. Prior to the bonding, the roughened surface of the copper oxide is treated with a solution such as benzotriazole, which complexes with the copper oxide to prevent formation of white spots and delamination as a result of such plating.

Protecting copper dielectric interface from delamination

A method of continuously regenerating a metal containing acid solution enhanced with a salt-free material. The metal dissolved in a bulk metal containing acid solution is continuously oxidized by introducing a gas into a packed reaction vessel. The packed reaction vessel is in operative relationship with the bulk acid solution for recirculating regenerated solution and for receiving spent solution. The gas is introduced substantially cocurrently with the spent acid solution.

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Johnson City, NY, United States of America

Lawrence Robert Blumberg