Stmicroelectronics Gmbh

Lawrence Philip Eng

Tsiu Chiu Chan

Arnaud Lepert

An apparatus and method for fabricating a microprocessor comprising a first chip () having an active face () including a central processing unit and a second chip () having an active face () electrically connected to the active face of the first chip (), wherein the second chip () provides added functionality to the central processing unit of the first chip () and wherein the electrical connections () are through bonding layers () that are in contact with the metalization 26 on the first and second chips (), is disclosed.

Stacked multi-component integrated circuit microprocessor

An apparatus and method for fabricating-a microprocessor comprising a first chip () having an active face () including a central processing unit and a second chip () having an active face () electrically connected to the active face of the first chip (), wherein the second chip () provides added functionality to the central processing unit of the first chip () and wherein the electrical connections () are through bonding layers () that are in contact with the metalizationon the first and second chips (), is disclosed.

A method and circuits for coupling a memory embedded in an integrated circuit to interconnect pads during a memory test mode is disclosed. The integrated circuit contains a processor, an embedded memory and a switching circuit for: (1) temporary coupling the interconnect pads of the integrated circuit, coupled to the processor during normal operation mode of the circuit, to the memory during a memory test mode; (2) and decoupling the external interconnect pads from the memory, after the memory is tested, and coupling them to the processor.

Testing of embedded memory by coupling the memory to input/output pads

A method and circuits for coupling a memory embedded in an integrated circuit to interconnect pads during a memory test mode is disclosed. The integrated circuit contains a processor, an embedded memory and a switching circuit for: (1) temporary coupling the memory array and memory peripheral circuits, coupled to the processor during normal operation mode of the circuit, to the interconnect pads of the memory during a memory test mode; (2) and decoupling the interconnect pads from the memory array and peripheral circuits, after the memory is tested, and coupling the memory array and peripheral circuits to the processor.

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Dallas, TX, United States of America

Lawrence Philip Eng