Intersil Americas Inc.

Intersil Corporation

Lawrence Pearce

Michael D Church

Donald Frank Hemmenway

Anthony L Rivoli

George V Rouse

George S Bajor

John W Butler

Jose Avelino Delgado

William David Bartlett

Alexander Kalnitsky

Thomas Andrew Jochum

Robert L Lyle, Jr

Nicolaas W Van Vonno

Harold William Satterfield

Michael Ray Jayne

A pulse-width modulated (PWM) DC-DC converter has a multitude of redundant channels supplying PWM signals to a voter whose output voltage controls the regulated DC output voltage. To ensure that single transient events, single permanent faults, or mismatches in the electrical characteristics of the various components disposed in the redundant channels do not adversely affect the regulated DC output voltage, transitions of the PWM signal in each channel are compared to the corresponding transitions of the voter's output signal. If a PWM signal transition of a redundant channel is detected as occurring relatively earlier/later than the corresponding transition of the voter's output signal, the width of the PWM signal is increased/decreased. If a PWM signal transition of a redundant channel is detected as occurring within a predefined window of the corresponding transition of the voter's output signal, the width of the PWM signal is not changed.

PWM voltage converter with redundancy and feedback adjustment

An integrated circuit includes a first and second diode connected in parallel. The first diode has a first breakdown voltage and has first P type region and first N type region adjacent to each other at the surface of the substrate of a substrate to form a lateral diode. The second diode has a second breakdown voltage less than the first breakdown voltage and has a second P type region and second N type region lateral adjacent to each other in the substrate to form a lateral diode below the surface The first and second N type regions overlap and the first and second P type region being electrically connected whereby the first and second diodes are in parallel.

Integrated circuit with a subsurface diode

A apparatus and method of operating a power converter circuit is provided. The method selectively couples control signals to at least one output driver stage of a plurality of output driver stages of the power converter circuit to obtain a desired output at a select output port of the plurality of output ports. Wherein each output driver stage has a defined current drive capacity that is output to the select output port in response to the control signals.

Power supply circuit containing multiple DC-DC converters having programmable output current capabilities

A power supply circuit contains a plurality of DC-DC converter control loops that provide respectively different control signals. A plurality of output driver stages of given current drive capabilities have their inputs programmably connectable via a set of switches to control signals that may be generated by any of the converter control loops. The output of each output driver stage is externally selectively connectable to any of plural output voltage ports, so that each output voltage port is capable of supplying any of the respectively different output voltages associated with the voltage control signals generated by the DC-DC converter control loops, and has an output current capability that depends upon which output driver stages are coupled to it.

Power supply circuit containing multiple DC&#x2014;DC converters having programmable output current capabilities

A digitally-implemented pulse width modulation (PWM) signal generator forms the PWM pulse width as a rational number based on full cycles of a PWM reference clock, and offers a very high effective resolution of the PWM pulse signal that is compatible with multiphase DC-DC converters. Being totally digital allows digital error accumulation and correction to occur at the point of origin of the PWM signal, well upstream of the relatively slow voltage control feedback loop. Quantization errors are corrected before they can accumulate in the converter's DC output voltage.

High resolution digital pulse width modulator for DC-DC voltage converter

In order to minimize switching-induced electromagnetic interference in a power supply switching circuit of the type used to control the AC power for multiple high voltage devices, such as cold cathode fluorescent lamps employed for backlighting a large scale liquid crystal display, the gating signals that are used to switch lamp-driving inverter circuits ON and OFF are staggered, or slightly offset in time, so that no two switching devices will be switched at the same time. By slightly offset in time is meant that the time differential between any pair of switching signals is relatively small compared to the period of the switching signal frequency. This has the effect of spreading out and thereby diminishing the magnitude of the spectral content of both capacitively and inductively coupled transients that are produced at switching times of the inverter circuits.

Staggering switching signals for multiple cold cathode fluorescent lamp backlighting system to reduce electromagnetic interference

A monolithicis mounted in a speaker cabinetto drive the voice coilof the speakerThe monolithic integrated circuit may be a class D amplifierand is at least a half-bridge or full bridge power MOSFET device. Structures and process for forming the mos switching devicesof the bridge driver circuits are disclosed. Also disclosed is the N+ buried layerof the QVDMOS transistorsof the bridge circuits.

Monolithic class D amplifier

In order to derive a precise measurement of temperature and current in a synchronous buck DC-DC converter a synchronous conduction cycle measurement of the value of reverse conduction voltage (V), and an asynchronous conduction cycle measurement of the value of body diode conduction voltage (V) of the low side power MOSFET are performed. These two measured values are then used as dual inputs to a two-dimensional to two-dimensional transform function (e.g., look-up table) that is effective to map the measured voltage values into output values for current (I) and temperature (T).

Technique for measuring temperature and current via a MOSFET of a synchronous buck voltage converter

An arrangement for measuring current through a phase section of a buck mode DC-DC converter includes an auxiliary integrated circuit containing an auxiliary power MOSFET and a pilot MOSFET coupled in parallel with a current path through a high side MOSFET of a half-bridge of the converter. The pilot MOSFET has a current path coupled to a current measurement terminal. The MOSFETs of the auxiliary circuit are time division multiplexed with the high side MOSFET, whereby a determination of current through the auxiliary high side MOSFET is based upon current through the pilot device and the geometric ratio of the size of the pilot device to that of the high side auxiliary MOSFET. The high side MOSFET is activated for a large number of switching cycles relative to the pilot circuitry, but the pilot circuitry is activated sufficiently often to derive a relatively accurate measure of current flow.

Time division multiplexed, piloted current monitoring in a switched mode DC&#x2014;DC voltage converter and phase current measurement calibration for a multiphase converter

A tapped delay line generates a fractional clock pulse signal for controlling a PWM pulse generator, such as used in a DC-DC converter. Operational parameters of the tapped delay are adjusted to maintain a desired fractional precision of the duty-cycle of the PWM clock pulse signal. In a first, phase locked loop (PLL) based embodiment, the tapped delay line-based digital PWM pulse generator includes a compensating phase locked-loop formed around an auxiliary tapped delay line that implements the voltage controlled oscillator of the PLL. In a second embodiment, the PWM pulse generator is configured as an 'open-loop' tapped delay line phase detector architecture, which avoids having to correlate parameters of the PLL delay line with those of the PWM delay line.

Robust fractional clock-based pulse generator for digital pulse width modulator

A low temperature coefficient resistor(TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor. The planned damage gives the TCRL a higher resistance without increasing its temperature coefficient. A process for fabrication of the resistor is used which combines separate spacer oxide depositions, provides buried layers having different diffusion coefficients, incorporates dual dielectric trench sidewalls that double as a polish stop, supplies a spacer structure that controls precisely the emitter-base dimension, and integrates bipolar and CMOS devices with negligible compromise to the features of either type.

BICMOS process with low temperature coefficient resistor (TCRL)

A low temperature coefficient resistor (TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor. The planned damage gives the TCRL a higher resistance without increasing its temperature coefficient. A process for fabrication of the resistor is used which combines separate spacer oxide depositions, provides buried layers having different diffusion coefficients, incorporates dual dielectric trench sidewalls that double as a polish stop, supplies a spacer structure that controls precisely the emitter-base dimension, and integrates bipolar and CMOS devices with negligible compromise to the features of either type.

BiCMOS process with low temperature coefficient resistor (TCRL)

An electronic device may include a circuit board, at least one load circuit carried by the circuit board, and a power distribution conductor carried by the circuit board and connected to the at least one load circuit. The electronic device may also include a multiphase switching regulator including a plurality of output stages connected to the power distribution conductor, and a controller for controlling the output stages based upon respective phase currents. The respective phase currents may be derived from corresponding voltage drops across the power distribution conductor and a matrix of resistivity values.

Growing community of inventors

Palm Bay, FL, United States of America

Lawrence Pearce