Seiko Epson Corporation

Lifebooster Inc.

Pmc-sierra, Inc.

Lawrence P Chee

Brett Anthony Cheng

David M Tucker

Barinder Singh Rai

Juraj Bystricky

Kevin Gillett

Neil Jason Lewis

David Mulvenna

John David Mulvenna

Sam Jaffari

Dan Robinson

Systems and methods are provided for evaluating workplace risk by associating sensors with individual members of a workforce to measure conditions affecting the individual. Data is obtained from the sensors for reoccurring work periods for each individual so that a risk analysis may be performed to derive a risk score. Probability of injury is calculated aggregating risk scores for multiple reoccurring work periods. The calculated probability of injury is used to quantify workplace risk for the at least one individual and an enterprise risk assessment is provided by combining the quantified risks for each individual.

Methods and systems for workplace risk assessment

Methods, systems and computer program products provide for a Risk Assessment Engine that receives body ambient temperature data captured by a sensor in contact with a person. The Risk Assessment Engine characterizes types of activities performed by the person during a time range associated with the body ambient temperature data. The Risk Assessment Engine determines a risk classification individualized for the person based on respective workloads and the corresponding allocations of work and rest experienced by the person during performance of the characterized types of activities.

Thermal stress risk assessment using body worn sensors

A method or system or apparatus provides improved data handling. In one aspect, destination scheduling is performed by scheduling polling rather than scheduling data emissions. In particular aspects, a scheduler assigns a weight and sequence number to each destination and tracks a port segment count and schedules polling of ports using these parameters.

Method and/or apparatus distributing variable-sized data units to variable destinations

A system for translating a portrait-oriented software address to a portrait-oriented yet landscape-configured display address. Based on the orientation of a display device, an address translation system either passes the software address 'as is' or translates the address to represent a portrait-oriented display address. A refresh address generator operates alternatively in column-forward and column-reverse modes, and additionally operates alternatively in row forward and row reverse modes to selectively rotate the image.

Display apparatus and method capable of rotating an image

A central processing unit (,) in a display system carries pixel-value signals and software-address signals representing the locations of the pixels whose values the pixel-value signals represent. An address-translation circuit (,) converts those software addresses to logical addresses representing the locations of those pixels in a 90&deg;-rotated version of the image that the software address signals represent, and the logical addresses are applied to an image-buffer memory (,) to specify the locations in which to store the pixel values. A refresh-address circuit (,) generates the address signals used in fetching from the image-buffer memory (,) the values that are applied to a display device (,) employed to display the image. The refresh-address generator (,) is operable alternatively in row-forward and row-reverse modes and alternatively in column-forward and column-reverse modes. The addresses represent a sequence of columns across rows and rows across an image, and the column addresses increase within a row in the column-forward mode but decrease in the column-reverse mode. The addresses increase between rows in the row-forward mode and decrease in the row-reverse mode. The effect of the different modes is to compensate for reversals such as mirror-image scans and to convert the 90&deg; rotation between clockwise and counterclockwise.

Display apparatus and method capable of rotating an image by 180 degrees

A computer system includes one or more display devices, such as a cathode ray tube (CRT) or liquid crystal display (LCD) for providing a visible display to a user of the computer system. The computer system includes a video display controller (VDC) with a graphics generator. This VDC receives image information, such as text or graphics generated by a processor (CPU) or retrieved by the CPU from another facility (such as a CD-ROM) of the computer system, and provides signals driving one or both of the CRT or LCD displays. The VDC includes a sequencer and controller (SEQC) for a dynamic random access memory (DRAM) which is interfaced with the VDC. The SEQC arbitrates requests from various devices of the computer system for access to the DRAM, and facilitates these access according to a multi-tiered priority scheme. Accordingly, more efficient access to the DRAM is insured for the various devices of the computer system, and utilization of the DRAM, as well as the time of devices which are sometimes required to wait for access to the DRAM is improved.

Apparatus and method having improved memory controller request handler

A display FIFO module is used in a DRAM interface. A low priority request and high priority request are both issued when the FIFO must receive new data or FIFO underrun will occur. This is determined by comparing the FIFO data level against a predetermined high threshold value. After a predetermined number of addresses have been latched by a DRAM controller sequencer to the DRAM for transferring data to the FIFO because of either the low or high priority request, or both, the display FIFO module reevaluates the FIFO data level to determine whether the FIFO data level is still below or is equal to either the low or high threshold value. If the FIFO data level is still below or equal to the low threshold value, the low priority request remains active; otherwise, the low priority request will be removed by the display FIFO module. Similarly, if the FIFO data level is still below or equal to the high threshold value, the high priority request remains active; otherwise, the high priority request will be removed by the display FIFO module.

Management of display FIFO requests for DRAM access wherein low priority

The present invention is directed to a display FIFO module for use in DRAM interface that includes a DRAM controller sequencer which prioritizes requests for DRAM access received from various modules, such as a CPU, a BitBLT engine module, and a half frame buffer logic module, etc. The display FIFO module issues low and high priority requests for DRAM access to the DRAM controller sequencer for loading the FIFO with display data to be transferred to the display device. The low priority request and high priority request are both issued when the FIFO must receive new data or FIFO underrun will occur. If the FIFO data level rises above the low threshold value, the low priority request will be removed by the display FIFO module. The hysteresis effect exhibited by the low priority request prevents it from being immediately re-asserted as soon as the FIFO level falls to the low threshold and prevents oscillation of the FIFO level about the low threshold value. The low priority threshold value is variable and is calculated such that the hysteresis time is substantially equal to the time required to service at least one other device n from the DRAM. This ensures that devices other than the display will utilize all of the DRAM availability time when it is not being used by the display.

Low priority FIFO request assignment for DRAM access

A power-down circuit (72) in a lap-top computer (10) cooperates with a separate monitor circuit (80) in each of a plurality of modules (68, 74, 76) that a video-display-controller integrated circuit (36) includes. In response to various stimuli, decoding logic (78) in the power-down circuit sends respective power-down-request signals to the various monitor circuits request permission to suppress application of respective clock signals to them. If a module's operational circuitry (82) is in a state in which clock removal is safe, the monitor circuit (80) responds with an acknowledgment signal, and the power-down circuit (72) causes a clock generator to interpret application of clock signals to the respective module (68). The monitor circuit (80) may additionally detect circumstances in which removing the clock signal from the operational circuitry (82) is safe only if the clock signal can subsequently be re-applied rapidly. In those circumstances, the monitor circuit (80) generates an idle signal that causes the power-down circuit (72) to stop clocking the associated operational circuitry but continue clocking the monitor circuit. In this way, the monitor circuit can keep operating so as to detect circumstances that will necessitate re-starting operational-circuit clocking. When it detects such a condition, it rapidly de-asserts the idle signal so that the clock signal is rapidly re-applied to the associated operational circuit.

Apparatus and method with improved power-down mode

A computer system includes an operator input device, a central processing unit (CPU), and a display device, such as a liquid crystal display (LCD) or cathode ray tube (CRT) providing a visible image to the computer user as an output of computer activity. The computer system includes a video display controller (VDC) with a graphics generator. This VDC receives image information, such as text or graphics generated by the CPU, or retrieved by the CPU from another facility (such as a CD-ROM) of the computer system, and responsively provides image signals driving the CRT or LCD display. The VDC includes a power saving controller implementing one of several available power saving modes dependent upon one or more of several possible inputs. Each of the power saving modes includes the same list of VDC functions which may individually be enabled or disabled in each power saving mode dependent upon a bit value entered into a register of the power saving controller. Each of the power saving modes is ranked with the others in an order of succession. Accordingly, when each mode of power saving is enabled, it disables the lower-ranked modes of power saving. In turn, each mode of power saving is disabled and succeeded if a higher-ranked mode is enabled.

Computer system with video display controller having power saving modes

A system and method for processing overlay display data. A display FIFO pipeline processes background graphics display data and a separate overlay FIFO pipeline processes overlay display data stored in an off-screen part of a graphics memory. The overlay FIFO pipeline performs format conversion, interpolation and scaling on the overlay display data and outputs it to an overlay mux. The overlay mux selects between the outputs of the display FIFO pipeline and the overlay FIFO pipeline in the processing of each scan line.

System and method for implementing an overlay pathway

A system and method recaptures peripheral device dedicated memory for use by other system components such as the CPU. The system comprises a CPU, a preferred primary PCI bridge and at least one peripheral system. The peripheral system comprises a peripheral device, a peripheral memory typically dedicated to the peripheral device, and a peripheral controller for managing peripheral device commands and peripheral memory access requests. The system may further comprise a system memory unit having a system memory and a system memory controller. The preferred primary PCI bridge couples the CPU to the peripheral system(s), determines dedicated and shared memory portions for the peripheral memory, creates a composite memory map, and delivers memory aperture information to each of the peripherals. During runtime, the preferred primary PCI bridge manages dedicated and shared peripheral memory access. Using the memory aperture information, each peripheral controller manages access to its respective peripheral memory.

System using a primary bridge to recapture shared portion of a

Computer system with efficient DRAM access

A computer system includes a dual-panel monochrome or color liquid crystal display (LCD). A dynamic random access memory (DRAM) of the computer includes a defined virtual memory array representative of pixel locations of the dual-panel LCD. Pixel values are read from the virtual array of the DRAM and written to corresponding locations of the display by a display pipeline. The writing of pixel values to the display proceeds pixel-by-pixel across a row of pixels in a panel, and then to the next row of pixels until a panel is refreshed. The panels of the array are refreshed one at a time alternating between an upper panel of the display and a lower panel of the display. While one panel is being refreshed, the other panel is blanked. Consequently, the dual-panel display may be driven with a simplified structure of display pipeline, and with a reduced time requirement for access to the DRAM.

Computer system with dual-panel LCD display

A computer system includes a pair of display devices, such as cathode ray tubes (CRT's) or liquid crystal displays (LCD's) for providing a visible display to a user of the computer system. The computer system includes a video display controller (VDC) providing for simultaneous display of different images on the pair of display devices. The VDC includes a display data processing circuit (DDPC) which is variably configurable to provide decoding of data words from a first bit-word format as received from a display first-in-first-out (FIFO) memory to a second bit-word format as required by a particular one of the pair of display devices. The DDPC is variably configurable to allow the pair of display devices to each receive driving signals providing the simultaneous differing images, and which driving signals originate with the bit-words allocated to each particular one of the pair of display devices. Accordingly, the DDPC simultaneously decodes bit-words from the first bit-word format to a pair of second bit-word formats, which second bit-word formats need not be the same, but can differ depending on the type of display device receiving the corresponding driving signals.

Growing community of inventors

Vancouver, Canada

Lawrence P Chee