International Business Machines Corporation

Lawrence P Andrews

John C Sinibaldi

Baiju Dhirajlal Mandalia

Kevin Bradley Williams

Judith Marie Linger

Oscar E Ortega

Joseph C Petty, Jr

Richard Clyde Beckman

Gordon Taylor Davis

Gary L Turbeville

Robert Chih-Tsin Eng

William R Robinson, Jr

Derrick L Arias

Chester A Heath

Laurence Victor Marks

Robert E Landa

Willie James Johnson

Joe Fletcher Jones, Jr

Richard G VanDuren

Christopher D Touch

Lee H House

Raymond Graham Fox

Clayton Potter Ludeman

Victor Anthony Scuderi

Thomas Wilbur Rounds, Jr

Douglas Howard Strait

Justin E Mead

Gary A Janes

A pair of communications adapters each include a number of digital signal processors and network interface circuits for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor. Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.

Apparatus including a host processor and communications adapters interconnected with a bus

The processing speed of a digital signal processor or system processor is controlled in accordance with the functions required in a task to be performed by the device, with these functions being compared to a table of maximum processing speeds at which various functions can be performed reliably by the device. This method is applied to a number of digital signal processors on a communications adapter, with a core kernel of each of these digital signal processors being driven at a processing speed controlled in this way, while peripheral functions of all these digital signal processors are performed according to a clock signal synchronized with data being received from a network transmission line.

Multi-speed DSP kernel and clock mechanism

Apparatus including a host processor and communications adapters

A pulse code modulation (PCM) unit is connected to a bus in a computer system. Also, connected to the bus is a processor and memory. The PCM unit is connected to transmit and receive telephone lines. The PCM unit reads uncompressed PCM data from the memory over the bus and compresses the PCM data for transmission over the telephone line in a cycle steal operation, wherein the bus is not being used by the processor. The PCM receives compressed PCM data from the receive telephone line, decompresses it, and writes the decompressed PCM data to the memory in a cycle steal operation. In addition, selectivity of either .mu.-Law or A-Law conversion, selectivity of even bit inversion for A-Law conversion, and selectivity between the compressed/decompressed PCM data or raw data is provided on a per channel basis. Selectable linear gain is also provided.

Pulse code modulation compression mechanism

In an communication system including a computer system comprising a digital signal processing adapter for performing a-set of tasks, and a E-1 port for providing and receiving time division multiplexed (TDM) signals in accordance with a first inter-system communication protocol, such as the E-1 or T-1 protocols, a communication subsystem, for coupling to the IP system. The communication subsystem includes an E-1 link for coupling to the first I/O port, and for providing and receiving TDM signals in accordance with the E-1 or T-1 protocols. The subsystem further includes a digital signal processor adapter, coupled to the second I/O port, for enhancing processing capability of the digital signal processing resource; and a third I/O port, coupled to the digital signal processor circuit, for providing and receiving signals in accordance with the first or a second inter-system communication protocol.

Expandable local inter-system bus architecture in a multiplexed

There is provided a Direct Access Memory Unit (DAu) that is associated with a remote processor module in a multi-processing system. The DAU performs Direct Memory Access (DMA) operations independently of a Central Processing Unit (CPU) in the remote processor module. The CPU requests a DMA by writing information relevant to the DMA to the remote processor's memory. The address of each control block is written to a circular queue, also in the remote processor's memory. The DAU determines if there are any control blocks to process and if so, the DAU will perform the DMA operation (reading data from or writing data to the memory of the host processor), all without the intervention of the CPU of the remote processor module. The CPU adds a new control block by loading its address in a location in the circular queue that is ahead of the circular queue location that the DAU is processing. The CPU can abort a pending DMA request during DAU operations by setting a skip bit in the control block. Upon the completion of performing a DMA request, the DAU will set a complete bit in the control block in the remote processor's memory. An interrupt can also be sent to the CPU, wherein the CPU is advised that a DMA request has been completed. The data in a DMA operation is sent in bursts to a buffer located between two busses having different data transmission rates.

Direct memory access unit for transferring data between processor

A multi-mode time division multiplexing (TDM) interface circuit for interfacing between a serial data port and a data buffer is provided. The TDM interface circuit contains a transmitter and a receiver section. The circuit is programmable to operate in a variety of modes and is capable of supporting various multi-channel TDM interfaces as well as single channel analog interfaces. The circuit is programmable by writing a control word to a control register. In operation the circuit receives a frame synchronization signal, a gated bit clock signal, and a bit clock signal from the circuit with which it is interfacing on the serial data port. A base address input to a base address register provides up to 9 of the most significant bits of a data buffer address. A 12-bit counter is used to generate the remaining (least significant) bits of the data buffer address according to the control word in the control register.

Multi-mode TDM interface circuit

A digital signal processing system includes first and second logical memory mapping units coupled to first and second digital processors respectively and to a data storage unit. The system further includes first and second mapping registers for containing first and second address mapping information coupled to the first and second digital processors respectively. The first and second mapping units are operative to receive (i) first and second logical addresses generated by the first and second digital processors respectively and (ii) first and second address mapping information respectively, and generate first and second physical addresses such that each of the digital processors can independently access any of a plurality of memory locations within the data storage unit.

Transparent memory mapping mechanism for a digital signal processing

An interprocessor interrupt hardware unit ('IIU') for processing interrupts between a remote processor and a host processor on a multiprocessor system. The IIU off loads tasks involved in processing interrupts from the operating kernel of the remote processor. Control blocks of interrupt information and commands are stored in Data Random Access Memory (DRAM) by the remote processor. The remote processor sets up a buffer of control block memory addresses in DRAM for the IIU to access to retrieve the control blocks from DRAM. The IIU retrieves a control block and loads the control block into registers. The IIU then issues an interrupt request to the host processor. The host processor receives the interrupt request and reads the registers to obtain the control block. The host processor clears the interrupt request and indicates to the IIU that the interrupt has been processed. The IIU then notifies the remote processor that the interrupt has been processed. The IIU may be programmed to notify the remote processor of completion either by an interrupt or by setting a status flag in the DRAM.

Interprocessor interrupt processing system

This I/O interface permits attachment of a data processing system to devices having different 'handshaking' protocols and bit-parallel data exchange capacities. Handshaking control circuits permit the system to communicate with devices variously in pulsed and interlocked modes. Timer circuits provide a variety of different time reference signals for transfer to devices. Switching options associated with the timer permit selective use of timer outputs as pulsed mode handshaking functions. A counter circuit and associated interface port permit the system to count events associated with device-originated pulses. A switching option permits the counter incrementing operations to be governed by timer outputs. The interface also contains path selection lines. In one mode these lines define high speed exchange of data between a primary system processor and devices in various bit-parallel formats and over various buses designatable by a systems processor. In another mode these lines permit a secondary system processor to exchange data with a series of multiplexed devices. Collectively, the interface lines have a symmetrical configuration which permits their use for direct interconnection of two data processing systems without the expense of additional 'channel to channel' adaptation.

Peripheral attachment interface for I/O controller having cycle steal

This disclosure is for an Audio-Visual training device having both a projectable film tape and an audio tape with control indicia on the audio tape in addition to recorded audio messages. The tape indicia are used to control a small processor which governs both tape and film movement. A keyboard on the device is used to enter replies to queries to a user from the tape and film and the processor will determine both tape and film movement in response to the answer to a query. The system is capable of multiway branching to present to the viewer the proper information pertaining to his answer. Several counters are available to count trials, correct or incorrect responses, etc., and to control tape and film movement in accordance with the counter readings. A proctor light may be turned on to call for personal assistance and to lock up the machine when a student is in trouble and the program does not have the proper branch to clear up the difficulty.

Interactive audio-visual instruction device

Growing community of inventors

Boca Raton, FL, United States of America

Lawrence P Andrews