Freescale Semiconductor,inc.

Motorola Corporation

Lawrence N Herr

James David Burnett

Douglas Michael Reber

Alexander Hoefler

Jinbang Tang

Marc Alan Mangrum

Kenneth R Burch

Darrel R Frear

Jong-Kai Lin

Robert E Booth

John David Porter

Bikas Maiti

Jack M Higman

Thomas W Liston

Glenn E Starnes

Glenn Charles Abeln

Tam Minh Tran

Mary Ann Coones

Rajesh R Kini

In a disclosed embodiment, a method for tiling selected vias in a semiconductor device having a plurality of vias comprises generating a layout database for the semiconductor device; creating zones around the plurality of vias; measuring density of covering metal in each zone; selecting a low density zone as being a zone that has a metal density less than a threshold metal density; and adding at least one tiling feature on a metal layer above the plurality of vias in the low density zone so that metal density of the low density zone increases to at least the same as the threshold metal density.

Method and apparatus to improve reliability of vias

A method for tiling selected vias in a semiconductor device is provided. The semiconductor device includes a plurality of vias. The method includes: generating a layout database for the semiconductor device; identifying isolated vias of the plurality of vias; selecting the isolated vias; defining a zone around each of the selected isolated vias; and adding tiling features on a metal layer above the selected isolated vias and within the zone. The method improves reliability of the semiconductor device by allowing moisture to vent from around the vias.

Methods and apparatus to improve reliability of isolated vias

An integrated circuit comprises a plurality of memory cells and an array supply voltage control circuit. The plurality of memory cells are organized in rows and columns. A row comprises a word line and all of the memory cells coupled to the word line. A column comprises a bit line pair and all of the memory cells coupled to the bit line pair. The array supply voltage control circuit is coupled to the plurality of memory cells. The array supply voltage control circuit is for receiving a power supply voltage and for providing a reduced power supply voltage to memory cells of a selected column during a write operation in response to a voltage differential on the bit line pair of the selected column.

Integrated circuit having an array supply voltage control circuit

Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.

Method of making an integrated circuit package with shielding via ring structure

A method includes forming a source, a drain, and a disposable gate () of the first transistor; forming a source, a drain, and a disposable gate of the second transistor; removing the disposable gates of the first transistor and the second transistor; forming a photoresist layer over the first transistor and the second transistor; patterning the photoresist layer to expose a gate region of the first transistor and a gate region of the second transistor; and implanting the substrate under the gate region of the first transistor and under the gate region of the second transistor, wherein implanting the substrate under the gate region of the first transistor provides a permanent shorting region between the source and the drain of the first transistor, and wherein implanting the substrate under the gate region of the second transistor adjusts a threshold voltage of the second transistor.

Method of forming an integrated circuit

A detect circuit may be used to detect one or more characteristics corresponding to the fuse being programmed. When the one or more characteristics of the fuse being programmed reach the desired states or values, the programming of the fuse is discontinued. Thus, the programming duration for each fuse is customized for each fuse. As a result, for some embodiments, there may be fewer fuses that have been over-programmed. In addition, for some embodiments, the range of impedances of the programmed fuses have a narrower distribution of impedances due to the use of the detect circuit.

Level detect circuit

Electromagnetic shield formation for integrated circuit die package

A two-port SRAM memory cell includes a pair of cross-coupled inverters coupled to storage nodes. An access transistor is coupled between each storage node and a write bit line and controlled by a write word line. The write word line is also coupled to a power supply terminal of the pair of cross-coupled inverters. During a write operation, the write word line is asserted. A voltage at the power supply terminal of the cross-coupled inverters follows the write word line voltage, thus making it easier for the stored logic state at the storage nodes to change, if necessary. At the end of the write operation, the write word line is de-asserted, allowing the cross-coupled inverters to function normally and hold the logic state of the storage node. Coupling the power supply node of the cross-coupled inverters allows faster write operations without harming cell stability.

Two-port SRAM having improved write operation

A method and apparatus for soft defect detection in a memory is disclosed. Bit lines are conditioned to predetermined voltages which ensure that, upon activation of the corresponding word line, all the storage transistors within the corresponding bit cells (at the intersection of the bit lines and the word line) are electrically conductive. A change in state of the bit cell in response to activation of the corresponding word line indicates the presence of a soft defect. An evaluator coupled to the memory may be used to identify defective memories by comparing the results of the testing to determine if any bit cells changed states. In one embodiment, the conditioning of the bit lines includes charging a bit line to a first predetermined voltage and its corresponding complementary bit line to a second predetermined voltage and then connecting the bit line and complementary bit line together to equalize the voltages.

Method and apparatus for soft defect detection in a memory

A method and apparatus for testing a static RAM includes a word line voltage control circuit (42) and an array supply voltage control circuit (46). In response to receiving a first control signal from a tester, the word line voltage control circuit (42) is used to provide a word line voltage to each word line of the memory array (31). The array supply voltage control circuit (46) provides a supply voltage to the array (31) in response to receiving a second control signal from the tester. During testing of memory 30, the array supply voltage and the word line voltage are supplied independently of the memory power supply voltage V.sub.DD in order to quickly detect memory cells that are defective due to soft defects.

Method and apparatus for testing a static RAM

An integrated circuit memory (114) has a power supply independent address buffer (50) that comprises an inverter (60), a bipolar transistor (67), and a P-channel transistor (68). The inverter (60) has an output terminal coupled to a base of the bipolar transistor (67). The P-channel transistor (63) is for injecting a current at the output terminal of the inverter in response to a reference voltage. The reference voltage varies proportionally to variations of a power supply voltage in order to compensate for gate-to-source voltage changes of a P-channel transistor (61) of the inverter (60) that occurs as a result of a changing power supply voltage. For address buffer (50), a range of address transition times as a function of power supply voltage is decreased, thus improving an address set-up and hold time of the integrated circuit memory (114).

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Coupland, TX, United States of America

Lawrence N Herr