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Mosel Vitelic Corporation

Lawrence Lee Aldrich

Kim Carver Hardee

John D Heightley

A base cell for a gate array or standard cell integrated circuit design has N and P wells organized in checkerboard fashion, each well containing several P and N devices respectively. A first of the plurality of relatively deep P regions is adjacent to at least a first and a second of the plurality of relatively deep N regions. The first relatively deep N region is adjacent to the first relatively deep P region along a first edge of the first relatively deep N region, and to the second relatively deep P region along a second edge of the relatively deep N region. The first and second edges of the relatively deep N region are perpendicular. An array of the base cells therefore has a checkerboard pattern, unlike the striped pattern of typical gate array and standard cell designs. The array of the base cells is amenable to minimizing clock parasitic capacitance when clocked inverters, including the complimentary clocked inverters of latches, are laid out at vertexes of the checkerboard pattern.

Base cell layout permitting rapid layout with minimum clock line capacitance on CMOS standard-cell and gate-array integrated circuits

An architecture for a high speed memory circuit having a relatively large number of internal data lines is shown to include global read and write data lines, and power and ground lines extending laterally across the array. The laterally extending lines are preferably within the third layer of metal. Preferably, the only other metal interconnect over the memory arrays is in the first metal layer, which is used to strap the word lines. Sense amp bands extend longitudinally along the borders of each memory cell bank. Local read and write data lines and read and write column select lines extend through the sense amp bands. Power and ground lines also extend through each sense amp band. Preferably, the architecture includes read path circuitry including a local read circuit that selectively isolates the global read data lines from the local read data lines. The architecture also preferably includes write path circuitry including a local write circuit that selectively isolates the global write data lines from the local write data lines. This architecture results in relatively low capacitance on the global read and write data lines, which permits faster data transfer speed with lower power requirements. It also results in relatively low resistance power and ground bussing, which further reduces the power requirements of the memory circuit.

Architecture for high speed memory circuit having a relatively large number of internal data lines

A reduced capacitance architecture for integrated circuits and particularly for memory integrated circuits is disclosed. The integrated circuit has a plurality of levels including first and second levels. A first signal conductor extends within the first level. A second signal conductor also extends within the first level and is positioned adjacent to and in close proximity with the first signal conductor. The second level is positioned adjacent to the first level and includes a third signal conductor extending within it. The third signal conductor is positioned laterally between the first and second conductors to eliminate vertical parallel plate capacitance.

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Colorado Springs, CO, United States of America

Lawrence Lee Aldrich