International Business Machines Corporation

Motorola Corporation

Lawrence Joseph Merkel

John Stephen Muhich

Derek E Williams

Kurt Alan Feiste

Ronald Xavier Arroyo

Bryan D Boatright

Christopher Bryant

Charles Gordon Wright

A data processing system and method having a number of cache controllers coupled to a bus. A cache controller uses a buffer operably coupled to the bus for loading information from the bus. A status bit associated with a buffer indicates the buffer status. The cache controller has logic circuitry operably coupled to the bus and the buffer. The logic circuitry responds to a certain cache coherency operation by loading the buffer and waiting during a predetermined interval for a possible retry signal before further processing the operation.

System and method for resolving contention arising from execution of

A first inverter includes a first input coupled to a first input node. Also, the first inverter includes a first output coupled to an output node. Further, the first inverter includes a voltage node. A second inverter includes a second input coupled to a second input node. Moreover, the second inverter includes a second output coupled to the voltage node.

Circuitry and method for gating information

A mechanism is provided in a microprocessor bus interface to eliminate the turnabout in those cases where the same slave is involved in consecutive read data bus tenures or where the same master and slave are involved in consecutive write data bus tenures. A new optional signal is added to the bus interface, called pre-last transfer acknowledge. The signal is asserted by the slave one cycle before the last transfer acknowledge signal is asserted. The signal is intended to be received by the system's bus arbiter. If the current data tenure and the next data tenure are both read operations directed to the same slave (such as the memory controller) or both write operations from the same master to the same slave, then the arbiter may grant the data bus to the master of the next data tenure the cycle following the assertion of the pre-last transfer acknowledge indicator. This allows the arbiter to grant the bus a cycle earlier than it normally could (where it would have to see the final transfer acknowledge signal before it could grant the bus). Thus, the bus turnaround cycle is eliminated and data bus bandwidth is increased by up to twenty percent.

Addition of pre-last transfer acknowledge signal to bus interface to

An arbitration protocol comprises the steps of receiving a plurality of resource request signals (12), comparing the received plurality of resource request signals to a rotating pointer (14), and either granting the shared resource to the resource user specified by the rotating pointer (16) and incrementing the rotating pointer (18) or granting the shared resource to a resource user according to fixed priority protocol (20, 22, 24, 26 and 28). The rotating pointer specifies one of a plurality of resource users according to a predetermined order. The two steps of granting are responsive to the step of comparing.

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Austin, TX, United States of America

Lawrence Joseph Merkel