Mips Technologies, Inc.

Mips Tech Limited

Lawrence Henry Hudepohl

Radhika Thekkath

Franz Treue

Darren Miller Jones

George Michael Uhler

Kevin D Kissell

G Michael Uhler

Vidya Rajagopalan

Majid Bemanian

David A Courtright

Scott Michael McCoy

Techniques are disclosed for processor synchronization within a reconfigurable computing environment for processor array redundancy. Processing elements are configured within a reconfigurable fabric to implement two or more redundant processors, where the two or more redundant processors are enabled for coincident operation. An agent is loaded on each of the two or more redundant processors, where the agent performs a function requiring data validation. The agent is fired on each of the two or more redundant processors to commence coincident operation. The coincident operation can include a lockstep operation. An output data result from each of the two or more redundant processors is compared to enable a data validation result. The data validation result is propagated. The propagating the data validation result can be based on comparing valid output data or can be based on comparing invalid output data.

Fail-safe semi-autonomous or autonomous vehicle processor array redundancy which permits an agent to perform a function based on comparing valid output from sets of redundant processors

A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between the CPU and one or more coprocessors.

Configurable co-processor interface

An interface for transferring data between a central processing unit (CPU) and a plurality of coprocessors is provided. The interface includes an instruction bus and a data bus. The instruction bus is configured to transfer instructions to the plurality of coprocessors in an instruction transfer order, where particular instructions designate and direct one of the plurality of coprocessors to transfer the data to/from the CPU. The data bus is configured to subsequently transfer the data. Data order signals within the data bus prescribe a data transfer order that differs from the instruction transfer order by prescribing a transfer corresponding to a specific outstanding particular instruction, where the data transfer order is relative to outstanding instructions. The outstanding instructions are those of the particular instructions transferred to the one of the plurality of coprocessors that have not completed a data transfer.

Configurable out-of-order data transfer in a coprocessor interface

A system accessible by a test access port controller via a test access port interface includes a data register. The data register is selectable based on an instruction register signal in the test access port interface. The instruction register signal is derived form an instruction register in the test access port controller. A shift register is connected to a data input and a data output in the test access port interface and to the data register. The operation of the shift register is controlled based on an indication of a state of a test access port controller state machine that is received over the test access port interface.

Distributed tap controller

A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

Tracing out-of order load data

Program counter and data tracing from a multi-issue processor

A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The interface groups signals that together comprises all the necessary information for a coprocessor to issue and execute instructions. Multiple issue groups are formed where each group supports different types of instructions, such as arithmetic instructions, or data transfer instructions. The coprocessor interface has an instruction transfer signal group for transferring different instructions from the CPU to the multi-issue coprocessor, sequentially or in parallel, an issue group designator for specifying an issue path within the multi-issue coprocessor for execution of the instructions, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instructions, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel.

Coprocessor interface transferring multiple instructions simultaneously along with issue path designation and/or issue order designation for the instructions

An apparatus and method are provided that enable a central processing unit (CPU) to extend the attributes of virtual memory beyond that which an existing translation lookaside buffer within the CPU is capable of storing while at the same time preserving compatibility with legacy operating system software. The apparatus includes a translation lookaside buffer and extended attributes logic. The translation lookaside buffer (TLB) stores a plurality of TLB entries. Each of the TLB entries has an extended memory attributes index field. The extended attributes logic is coupled to the TLB. The extended attributes logic employs the extended memory attributes index field to access one of a plurality of extended memory attributes registers that is external to the TLB. Contents of the extended memory attributes register prescribe specific extended properties for a corresponding virtual memory page. The extended memory attributes index field is a field that is also employed by a legacy memory management protocol to prescribe legacy properties. The plurality of extended attributes registers are initialized to states that correspond to the legacy properties so that the CPU is compatible with operating systems employing the legacy memory management protocol.

Growing community of inventors

Saratoga, CA, United States of America

Lawrence Henry Hudepohl