Northern Telecom Limited

Lawrence H Sasaki

Stephen Kenneth Sunter

Anthony K Brown

Ronald G Wellard

Sun-Shiu D Chan

Nicholas Tsiakas

An apparatus includes an IC chip with a signal transmitter and an IC chip with a signal receiver, both chips being mounted on a printed circuit board and being connected via conductors on the board. The signal transmitter has a voltage-current converter and a high output impedance current amplifier. The signal receiver has a current-voltage converter. The voltage-current converter converts the voltage of the digital signal to current which in turn is amplified by the high output impedance current amplifier. The amplified current flows via the conductors in the receiver. The digital signal is transferred via the conductors on the current basis. Due to the transmission of the digital signal of current from the signal transmitter to the signal receiver via the conductors, signal spikes while transmitting are reduced and noise immunity is improved. Also, EMI (electromagnetic interference) emission is reduced and power dissipation is small.

Signal receiver and apparatus incorporating same

A low power (10 mW), high-speed (50 Mb/s) digital driver is formed from three analogue components: level shifter to limit the output swing, waveshaper to limit the slew-rate of the output transition, and a Class AB output stage to buffer the signal. The components afford flexibility to meet the demands of different applications. The driver can be limited to 1V swing for terminated applications such as for backplanes, or it can be limited to 1V swing for unterminated applications such as intraboard (PCB) communication.

Digital driver with class AB output stage

A scaler comprising a plurality of flip-flops, varies its frequency division to correct phase by 0.5 clock cycle. Each flip-flop is continuously and synchronously responsive to either a rising or a falling edge of the clock pulses. Normally, the scaler's state transits along one of two loops, which generate output pulses having identical repetition rates. When a control signal is applied, the scaler's state transits from one loop to the other, generating at least one output at an alternative repetition rate. The alternative repetition rate is either lower or higher than the identical repetition rate by an integral number of half cycles of the input clock pulses. Where there are two control signals, a lower or higher alternative repetition rate can be selected. Since the flip-flops are responsive to either edge of the clock pulses without clock gating interruptions, there is no jitter and the scaler's robustness is improved. Also the clock frequency can be effectively halved.

Scaler for synchronous digital clock

Bidirectional communication of voice and data signals over a two wire telephone line interconnecting several telephone sets with a digital access circuit of a central data and voice communication facility is achieved by a frequency division multiplexing circuit that functions either as a set interface for a telephone or as a line card interface for the access circuit. Data message signals input to the multiplexing circuit are stored in a shift register for subsequent modulation of a carrier signal, but since only one interface may enter a transmission mode at one time transmission priority is assigned by a controller to the interface that first attempts transmission on an inactive line. All other interface then enter a monitor mode to listen but not act on the transmitted message. Transmission errors caused by line noise, or collision transmissions between two or more interfaces are resolved via message transactions between the interfaces only, and retransmission priority is resolved in favor of an interface having the lowest address. Controllable transmit and receive equalizers define analog signal paths in the interfaces and compensate for line losses.

Growing community of inventors

Manotick, Canada

Lawrence H Sasaki