International Business Machines Corporation

Lawrence Dean Whitley

John Michael Borkenhagen

Danny Marvin Neal

Harvey Gene Kiel

Richard Allen Kelley

Adalberto Guillermo Yanes

Brian Thomas Vanderpool

Glen R Mitchell

Richard G Mustain

Jon H Peterson

Ricky Merle Peterson

In a method of controlling stores to and reads from a cache, if a read request is in a read queue, then a read is performed. If no read is in the read queue and if a store request is in a store queue and if an early read predict signal is not asserted, then a store is performed. If no read is in the read queue and if a store request is in the store queue and if the early read predict signal is asserted, if a read is detected a read is then performed. Otherwise, if the early read predict is subsequently de-asserted, then a store is performed.

Read prediction algorithm to provide low latency reads with SDRAM cache

Buffer management for improved PCI-X or PCI bridge performance. A system and method for managing transactions across a PCI-X or PCI bridge, and a system and method of waiting for, increasing, and/or optimizing the available buffers for transaction size or sizes across a PCI-X or PCI bridge. Transactions are processed across the bridge, and the bridge has buffers with actual available buffer space used for receiving and processing the transactions. Transaction size of the transaction is determined. The system and method sets an available free block which is a set amount of available buffer space that is to be freed up before certain larger size transactions are processed. The system and method waits for the actual available buffer space to free up to and reach the available free block. The certain larger size transactions are then processed when the actual available buffer space has reached the available free block. The processing of the transaction involves accepting the transaction if the transaction size is not greater than the actual available buffer space, retrying the transaction for processing by the bridge when the transaction size is less than the available free block but greater than the actual available buffer space, retrying the transaction by the bridge when the transaction size is greater than the available free block and greater than the available buffer space until the available buffer space is greater than or equal to the available free block, and accepting the transaction and then disconnecting once the actual available buffers are filled or at an end of the transaction.

Buffer management for improved PCI-X or PCI bridge performance

A workstation controller is disclosed which operates in either full screen write mode or partial screen write mode. In one embodiment, the controller looks for a 'Clear Display'(CD) command in the data stream from the host. If the data stream contains a CD command and if a screen image buffer is available, the controller operates in full screen write mode. Subsequent 'Write to Device' (WTD) commands in the data stream are sent to the buffer, not to the device. When the controller detects the end of the data stream the entire contents of the buffer are sent to the display in one operation. If the controller does not detect a CD command in the data stream, or if the CD command is detected but a screen image buffer is not available, the controller operates in partial screen write mode. WTD commands in the data stream are sent directly to the display one at a time.

Workstation controller with full screen write mode and partial screen

In a processor having a real address space larger than its virtual address space, all of the physical memory is addressed by using a separate prefix register associated with each of the address registers to hold both a high-order address portion and a control bit specifying whether the address is to be translated or used as a direct real address.

Directed address generation for virtual-address data processors

Multi-level indexed indirect addressing is provided with matched pairs of prefix bytes and suffix values which can surround any instruction. Each prefix code is distinguishable from an instruction code. Counters keep track of indirection levels.

Growing community of inventors

Rochester, MN, United States of America

Lawrence Dean Whitley