International Business Machines Corporation

Lawrence D Curley

Patrick James Meaney

Glenn David Gilda

John Steven Dodson

Gary A Van Huben

Eric Eugene Retter

Michael Andrew Blake

Christopher J Berry

Vesselina K Papazova

Garrett M Drapala

William Robert Lee

Scot H Rider

Dennis P Cheney

Irving G Baysah

Ronald S Svec

James Charles Gregerson

Charles John Stein

George C Wellwood

Leland D Richardson

Travis Wellington Pouarz

Timothy Carl Bronson

Craig Raymond Walters

Agnes Yee Ngai

Eric M Foster

Tobias Webel

Thomas Edward Rosser

Charles E Boice

Diana Lynn Orf

John Mark Kaczmarczyk

Arjen Alexander Mets

Ulrich Baur

Ralf Ludewig

William J Scarpero, Jr

Everett G Vail, Iii

Ronald J Frishmuth

Jose Luis Pontes Correia Neves

James F Driftmyer

Ching Lung Tong

Matthew J Mitchell, Jr

John Mack Isakson

Edward J Kaminski

Kristen M Tucker

Embodiments relate to performing a memory scrubbing operation that includes injecting an error on a write operation associated with a memory address. One or more errors are detected during a two-pass scrub operation on the memory address. Based on a result of the two-pass scrub operation, one or more of a hard error counter associated with the memory address and a soft error counter associated with the memory address is selected. The one or more selected counters are updated based on the result of the two-pass scrub operation.

Error injection and error counting during memory scrubbing operations

Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (CPU) chip. In this type of on-chip embodiment, the address incrementing utility utilizes dedicated hardware, chip-resident firmware, and one or more memory address configuration maps to enhance processing speed, efficiency and accuracy. The combined rank and linear memory address incrementing utility is designed to efficiently increment through all of the individual bit addresses for a large logical memory space divided into a number of ranks on a rank-by-rank basis. The address incrementing utility sequentially generates all of the sequential memory addresses for a selected rank, and then moves to the next rank and sequentially generates all of the memory addresses for that rank, and so forth until of the ranks have been processed.

Combined rank and linear address incrementing utility for computer memory test operations

A computer-system implemented method for dual asynchronous and synchronous memory operation in a memory subsystem includes establishing a synchronous channel between a memory controller and a memory buffer chip. A mode selector determines a reference clock source for a memory domain phase-locked loop of the memory buffer chip based on an operating mode of the memory buffer chip. An output of a nest domain phase-locked loop is provided as the reference clock source to the memory domain phase-locked loop in the memory buffer chip based on the operating mode being synchronous. The nest domain phase-locked loop is operable synchronous to a memory controller phase-locked loop of the memory controller. A separate reference clock is provided independent of the nest domain phase-locked loop as the reference clock to the memory domain phase-locked loop based on the operating mode being asynchronous.

Dual asynchronous and synchronous memory system

Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains.

Serializing instructions in a multiprocessor system includes receiving a plurality of processor requests at a central point in the multiprocessor system. Each of the plurality of processor requests includes a needs register having a requestor needs switch and a resource needs switch. The method also includes establishing a tail switch indicating the presence of the plurality of processor requests at the central point, establishing a sequential order of the plurality of processor requests, and processing the plurality of processor requests at the central point in the sequential order.

Centralized serialization of requests in a multiprocessor system

An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.

Integrated circuit arrangement for test inputs

Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of the cache line receiving compute nodes, including, if the cache line is missing from a compute node, an indication whether that compute node has cache storage space available for the cache line; determining by the first compute node, according to the states of the cache line and space available, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes.

Horizontal cache persistence in a multi-compute node, symmetric multiprocessing computer

A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains and stumps are optimized by dividing an area encompassed by the chains and by a start point and an end point of the stump into a grid comprised of a plurality of grid boxes, and determining a grid box to grid box connectivity route to access all of the grid boxes between the start point and the end point by means of a computer running a routing algorithm. All other chains and stumps are optimized randomly assigning to a stump a chain that can be physically reached by that stump and adding an additional chain to that stump based on the number of latches in the additional chain, its physical location, and the number of latches already assigned.

Method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy

A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.

Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuit

The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.

Method of automating creation of a clock control distribution network in an integrated circuit floorplan

A processing facility is provided for simultaneously receiving multiple streams of digital audio data and based thereon concurrently outputting both an unmixed digital audio signal and a mixed digital audio signal. The processing facility can be implemented, for example, within an audio decoder of a set top box. The facility includes receiving a first stream of digital audio data and a second stream of digital audio data, and outputting the first stream of digital audio data as an unmixed digital audio signal. Simultaneous therewith, the first stream of digital audio data and the second stream of digital audio data are digitally mixed and outputted as a mixed digital audio signal. If necessary, the second stream of digital audio data is redigitized based on a sample frequency of the first stream of digital audio data, and either or both the first stream and second stream of digital audio data are decoded prior to mixing.

Facility for simultaneously outputting both a mixed digital audio signal and an unmixed digital audio signal multiple concurrently received streams of digital audio data

An integrated digital video system is configured to implement picture-in-picture merging of video signals from two or more video sources, as well as selective overlaying of on-screen display graphics onto the resultant merged signal. The picture-in-picture signal is produced for display by a television system otherwise lacking picture-in-picture capability. The digital video system can be implemented, for example, as an integrated decode system within a digital video set-top box or a digital video disc player. In one implementation, a decompressed digital video signal is downscaled and merged with an uncompressed video signal to produce the multi-screen display. The uncompressed video signal can comprise either analog or digital video. OSD graphics can be combined within the integrated system with the resultant multi-screen display or only with a received uncompressed analog video signal.

Integrated video processing system having multiple video sources and implementing picture-in-picture with on-screen display graphics

A programmable bi-directional external graphics/video (EGV) port for a video decode system chip having a video decoder and an internal digital display generator circuit is provided. The programmable EGV port employs a fixed number of signal input/output (I/O) pins on the video decode system chip while providing a plurality of connection configurations for an external graphics controller, an external digital display generator circuit and an external digital multi-standard decoder to the video decoder or the internal digital display generator circuit of the chip. The EGV port includes receiver/driver circuitry for accommodating in parallel a plurality of input/output signals, including pixel data signals and corresponding synchronization signals, as well as a programmable port controller adapted to be coupled between the receiver/driver circuitry and an internal bus of the video decode system allowing access to at least one of the video decoder and the internal digital display generator circuit. The programmable port controller is programmable to either receive data into the video decode system chip or to send data out from the video decode system chip.

Programmable external graphics/video port for digital video decode system chip

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Endwell, NY, United States of America

Lawrence D Curley