Taiwan Semiconductor Manufacturing Comp. Ltd.

Lawrence Chiang Sheu

Chen-Hua Douglas Yu

Chih-Hang Tung

Tung-Liang Shao

Yi-Li Hsiao

Hao-Yi Tsai

Chih-Hsin Ko

Kuo-Chung Yee

Hun-Jan Tao

Ming-Che Ho

Chun-Chieh Lin

Yeong-Jyh Lin

Chien-Hsiun Lee

Jean Wang

Baw-Ching Perng

Chia-Hsiang Lin

Yi-Chun Huang

Chun Hui Yu

Liang-Ju Yen

Bow-Wen Chan

An apparatus includes a semiconductor component and a cooling structure. The cooling structure is over a back side of the semiconductor component. The cooling structure includes a housing, a liquid delivery device and a gas exhaust device. The housing includes a cooling space adjacent to the semiconductor component. The liquid delivery device is connected to an inlet of the housing and is configured to deliver a liquid coolant into the cooling space from the inlet. The gas exhaust device is connected to an outlet of the housing and is configured to lower a pressure in the housing.

Method for forming a semiconductor component with a cooling structure

Semiconductor component with cooling structure

An integrated circuit structure includes a substrate and a metal pad over the substrate. A post-passivation interconnect (PPI) line is connected to the metal pad, wherein the PPI line includes at least a portion over the metal pad. A PPI pad is connected to the PPI line. A polymer layer is over the PPI line and the PPI pad, wherein the polymer layer has a thickness greater than about 30 &#x3bc;m. An under-bump metallurgy (UBM) extends into an opening in the polymer layer and electrically connected to the PPI pad.

Solder ball protection structure with thick polymer layer

A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer.

Method of forming interconnects for three dimensional integrated circuit

A method for manufacturing integrated circuits on a wafer includes providing a facility-supplied room temperature solution; controlling the temperature of the facility-supplied room temperature solution to a desired temperature set point to generate a rinse solution; and rinsing a polishing pad using the rinse solution. The wafer is then polished by means of a chemical mechanical polishing process.

CMP by controlling polish temperature

A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

Recessed polysilicon gate structure for a strained silicon MOSFET device

Growing community of inventors

Hsin-Chu, Taiwan

Lawrence Chiang Sheu