Credo Technology Group Limited

Credo Semiconductor (hong Kong) Limited

Lawrence Chi Fung Cheng

Runsheng He

Yifei Dai

Xike Liu

Chan Ho Yeung

Kuan Peng

Haoli Qian

Junqing Phil Sun

Rajan Pai

Haihui Luo

Joe Sheredy

Integrated circuits such as multi-channel receivers may require loop inductors resistant to electromagnetic field interference. Such loop inductors may include multiple non-overlapping loops each defining a corresponding dipole, the multiple dipoles summing to zero, with at least one of said loops having unequal areas. The multiple non-overlapping loops may include: a center loop defining a central magnetic dipole; and a plurality of peripheral loops equally spaced around a perimeter of the center loop, each peripheral loop defining a peripheral magnetic dipole oriented opposite the central magnetic dipole, the plurality of peripheral loops substantially canceling a field from the central magnetic dipole. The total number of loops may be odd, with particular embodiments of three, five, and seven loop designs disclosed. Single and multi-turn embodiments are provided.

Enhanced inductors suitable for integrated multi-channel receivers

Mass-manufactured cables suitable for large communication centers may convert from differential PAM4 interface signaling to parallel single-ended NRZ transit signaling at 53.125 GBd to provide bidirectional data rates up to 800 Gbps and beyond. One illustrative cable embodiment includes: electrical conductors connected between a first connector and a second connector, each adapted to fit into an Ethernet port of a corresponding host device to receive an electrical input signal to the cable conveying an outbound data stream from the host device and to provide an electrical output signal from the cable conveying an inbound data stream to that host device. The electrical input and output signals employ differential PAM4 modulation to convey the inbound and outbound data streams. Each of the first and second connectors includes transceivers to perform clock and data recovery on the electrical input signal to extract and re-modulate the outbound data stream for transit via the electrical conductors as respective pairs of electrical transit signals employing single-ended NRZ modulation.

Single-ended signaling between differential ethernet interfaces

Modular layout design units are provided with an internal channel for multi-directional distribution of a shared signal. In one illustrative embodiment, an integrated circuit includes: one or more modular units, each modular unit having an internal channel for signal distribution. The internal channel possesses: an edge connection on each edge of the modular unit; a hub node coupled to each edge connection by a respective bi-directional buffer having an incoming buffer and an outgoing buffer with at least one of the incoming and outgoing buffers disabled, the bi-directional buffers cooperating to steer a signal from a selectable one of the edge connections to one or more of the other edge connections; and a tap providing the signal for use by internal circuitry of the modular unit.

IC layout tiles with internal channel for signal distribution

High-data rate channel interface modules and equalization methods employing a finite impulse response (FIR) analog receive filter. Embodiments include an illustrative channel interface module having multiple amplifier-based delay units arranged in a sequential chain to convert an analog input signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog input signal to form an equalized signal; and a symbol decision element operating on the equalized signal to obtain a sequence of symbol decisions. An interface that extracts received data from the sequence of symbol decisions. The delay units may employ one or more delay cells each having a common-source amplifier stage followed by a source follower output stage, the two stages providing approximately equal portions of the propagation delay. An enhanced gate-to-drain capacitance in the common-source amplifier may increase propagation delay while reducing bandwidth limitations.

Finite impulse response analog receive filter with amplifier-based delay chain

An illustrative multi-lane communication method includes: (a) receiving receive signals on different receive channels; (b) converting each of the receive signals into a lane of a multi-lane receive data stream, wherein said converting includes demodulation and error measurement; (c) determining remote pre-equalizer adaptation information based in part on the error measurement; (d) detecting alignment markers in the multi-lane receive data stream; (e) extracting local pre-equalizer adaptation information in, or proximate to, the alignment markers in the multi-lane receive data stream; (f) using the local pre-equalizer adaptation information to adjust coefficients of a local pre-equalization filter; (g) periodically inserting an alignment marker in a multi-lane transmit data stream, wherein the remote pre-equalizer adaption information is included in, or inserted proximate to, the alignment markers; and (h) transforming each lane of the multi-lane transmit data stream into a transmit signal, wherein said transforming includes modulating and applying the local pre-equalization filter.

Low power SerDes architecture and protocol

Disclosed is at least one flash analog-to-digital converter embodiment having a linear voltage ladder, a set of comparators each of which is coupled to one or more operational amplifiers by a sampling switch. Each of the sampling switches samples the comparator output, using the parasitic capacitance of the operational amplifier to hold the voltage. The sampling switches may be single transistors. Some embodiments further include, for each comparator, multiple operational amplifiers each of which drives a binary latch via a gating switch. The gating switches operate in sequence to distribute sequential samples to different latches. At least some embodiments of the flash converter further include an automatic gain control (AGC) that has both differential input terminals and differential output terminals. In such embodiments the comparators compare the differential output of the AGC to a differential reference voltage, and may further provide the result as a differential signal.

Growing community of inventors

San Jose, CA, United States of America

Lawrence Chi Fung Cheng