International Business Machines Corporation

Stmicroelectronics Gmbh

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Infineon Technologies Ag

Other

Globalfoundries Singapore Pte. Ltd.

Elpis Technologies Inc.

Adeia Semiconductor Solutions LLC

Samsung Electronics Co., Ltd.

Freescale Semiconductor,inc.

Chartered Semiconductor Manufacturing Ltd (corporation)

Kyndryl, Inc.

Tessera LLC

Internatoinal Business Machines Corporation

Lawrence Alfred Clevenger

Michael Rizzolo

Benjamin David Briggs

Carl John Radens

Chih-Chao Yang

Christopher J Penny

Nicholas Anthony Lanzillo

John H Zhang

Timothy Joseph Dalton

Louis L Hsu

Brent A Anderson

Robert Russell Robison

Junli Wang

Baozhen Li

Kangguo Cheng

Kisik Choi

Terry Allen Spooner

Hosadurga K Shobha

Kirk David Peterson

Ruilong Xie

Theodorus E Standaert

Keith Kwong Hon Wong

Matthew Earl Colburn

Sivananda K Kanakasabapathy

Takashi Ando

Hsueh-Chung Chen

Cyril Cabral, Jr

Kevin Shawn Petrarca

Koichi Motoyama

Yann Mignot

Louis Lu-Chen Hsu

Fee Li Lie

Joshua M Rubin

John Edward Sheets, Ii

Jonathan Hudson Connell, Ii

Nalini Kanta Ratha

Balasubramanian Pranatharthiharan

Takeshi Nogami

Satyanarayana Venkata Nitta

Zhenxing Bi

Zhengwen O Li

Dureseti Chidambarrao

Reinaldo Ariel Vega

Yuk Lung Chan

Elbert Emin Huang

Jack Allan Mandelman

Sampath Purushothaman

Ekmini Anuja De Silva

Qinghuang Lin

Wai-Kin Li

Richard Stephan Wise

Su Chen Fan

Andrew Herbert Simon

Ronald G Filippi

Gregory J Boss

Huilong Zhu

Nicolas J Loubet

John Elbert Moore, Jr

Julien Frougier

Zheng Xu

Andrew R Jones

Charles Leon Arvin

Kevin Charles Mcconnell

Marc Adam Bergendahl

Omer H Dokumaci

Griselda Bonilla

Xiao Hu Liu

Jeffrey P Gambino

Tenko Yamashita

Chen Zhang

Dechao Guo

Shom Ponoth

Ruqiang Bao

Timothy Dooling Sullivan

Kenneth Parker Rodbell

Arvind Kumar

Thomas M Shaw

Conal Eugene Murray

Bruce Bennett Doris

Veeraraghavan S Basker

Clement Hsingjen Wann

Chanro Park

Oleg Gluschenkov

Hemanth Jagannathan

Mukta G Farooq

Soon-Cheon Seo

Katherine Lynn Saenger

Michael Patrick Chudzik

Laertis Economikos

Effendi Leobandung

Chung H Lam

Daniel C Edelstein

Shogo Mochizuki

Yun Yu Wang

Lars W Liebmann

Son Van Nguyen

Terence B Hook

Christian Lavoie

Injo Ok

Chandrasekharan Kothandaraman

One or more systems, devices and/or methods of use provided herein relate to an airgap spacer for power via. The semiconductor device can comprise a power bar wired to a backside power rail, wherein the power bar is located between a first gate of a first field effect transistor (FET) and a second gate of a second FET at least a first airgap between the power bar and at least a portion of the first gate of the first FET and a second airgap between the power bar and at least a portion of the second gate of the second FET, wherein the at least the first airgap and the second airgap maintain parasitic capacitance in the semiconductor device below a threshold.

Airgap spacer for power via

A semiconductor structure includes logic device and passive device regions. The logic device region includes field effect transistors (FETs) having a gate structure and a source/drain region disposed on opposing sides of the gate structure. At least one source/drain region extends within a buried dielectric layer for electrically connecting a FET to a backside power rail (BPR). The passive device region includes passive devices disposed on a first side of a first semiconductor layer. A second semiconductor layer is disposed above a second side of the first semiconductor layer opposing the first side. A backside interlevel dielectric (BILD) is above the second semiconductor layer and the buried dielectric layer. The BPR is embedded within the BILD in the logic device region. A top surface of the BILD in the passive device region is coplanar with a top surface of the BPR and the BILD in the logic device region.

Semiconductor passive device integration for silicon-on-insulator substrate

A semiconductor structure and method of manufacturing a semiconductor structure having a front side and an opposing backside. An early power delivery network (EBPDN) of wires is built above a substrate layer. Buried power rails (BPRs) are built above levels of the PDN and connected to the EBPDN by short length via connections that can be self-aligned to the back side buried power rails. Both BPRs and vias connections have a common metallization. A front side level of transistor devices are built at the front side of the structure above the BPRs. The resulting formed buried power rail structure has an aspect ratio of height:width greater than 4:1, a height >3 times a height of the formed via structure; and a via structure having a length greater than a height of the formed conductive power rail structure.

Early backside first power delivery network

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a semiconductor wafer having a first transistor and a second transistor; a first source/drain (S/D) contact of the first transistor; a second S/D contact of the second transistor; and a cut region between the first S/D contact and the second S/D contact, wherein the cut region includes a liner of a first dielectric material and a filler of a second dielectric material that is different from the first dielectric material, the liner lining at least a part of the first S/D contact and a part of the second S/D contact, and the filler being directly adjacent to the liner and between the first S/D contact and the second S/D contact. A method of manufacturing the semiconductor structure is also provided.

Source/drain contact at tight cell boundary

Semiconductor devices including a super via connection between levels are provided. The semiconductor device can include a first interlevel dielectric layer, a back-end-of-line (BEOL) interconnect structure disposed in the first interlevel dielectric layer, a second interlevel dielectric layer disposed on a first portion of the first interlevel dielectric layer, a third interlevel dielectric layer disposed on the second interlevel dielectric layer, and a super via disposed on a second portion of the first interlevel dielectric layer, wherein a first end of the super via is connected to the BEOL interconnect structures and wherein a second end of the super via opposite the first end of the super via is a distance from the first interlevel dielectric layer larger than a height distance of the second interlevel dielectric layer.

BEOL interconnect subtractive etch super via

A microelectronic structure comprises a first interconnect line at a first interconnect level, a second interconnect line at a second interconnect level, and at least one via connecting the first interconnect line at the first interconnect level to the second interconnect line at the second interconnect level. The at least one via comprises a vertical section and at least one horizontal section, the at least one horizontal section being in contact with at least a portion of one of a top surface of the first interconnect line and a bottom surface of the second interconnect line.

Interconnect structures with vias having vertical and horizontal sections

A semiconductor structure comprises an active device stack comprising one or more layers, the one or more layers comprising a top electrode. The semiconductor structure also comprises an additional layer disposed over the active device stack, an encapsulation layer surrounding the active device stack and the additional layer, and a contact to the top electrode coupled to the additional layer.

Metal hard mask integration for active device structures

A structure is provided that includes a first metal level including a first metal line, a second metal level spaced apart from the first metal level and including a second metal line, and a first metal via structure connecting the first metal line to the second metal line. The first metal via structure directly contacts a sidewall surface and a horizontal surface of the first metal line.

Wrap around metal via structure

A vertical transport field effect transistor (VTFET) apparatus includes a fin-shaped channel structure; a gate stack that surrounds the channel structure; a top source/drain structure at a top end of the channel structure; a top interconnect layer above the top source/drain structure; a top contact that electrically connects the top source/drain structure to the top interconnect layer; a bottom source/drain structure at a bottom end of the channel structure; a backside interconnect layer below the bottom source/drain structure; and a backside contact that touches a bottom surface of the bottom source/drain structure and also touches a side surface of the bottom source/drain structure and electrically connects the bottom source/drain structure to the backside interconnect layer.

Vertical transport field effect transistor (VTFET) with backside wraparound contact

A back side contact structure is provided that directly connects a first electrode of a MRAM, which is present in a back side of a wafer, to a source/drain structure of a transistor. The back side contact is self-aligned to the source/drain structure of the transistor as well as to the first electrode of the MRAM. The close proximity between the MRAM and the source/drain structure increases the speed of the device. MRAM yield is not compromised since no re-sputtering of back side contact metal onto the MRAM occurs.

MRAM integration with self-aligned direct back side contact

An IC memory device includes a substrate and an array of memory cells on the substrate. Each memory cell includes at least one memory cell transistor in a layer of the device adjacent to the substrate. In the same layer, the device also includes a plurality of shunt transistors. The device also includes a buried metal signal rail, which is disposed between the array of memory cells and the plurality of shunt transistors in a buried layer that is embedded into the substrate below the transistors. The device also includes single-layer vias, which are in same layer as the transistors and electrically connect the memory cell transistors to the shunt transistors through the buried metal signal rail.

Buried metal signal rail for memory arrays

A dual structure buried rail includes an upper rail and a lower rail. The upper rail may be inset relative to the lower rail. In other words, the lower rail may be wider than the upper rail, and/or the lower rail may have a larger geometrical volume than the upper rail. The upper rail may be located at a boundary of, and/or directly next to, an active device region and the lower rail may extend directly underneath at least a portion of the active device region. The lower rail may extend the entire length of the upper rail. The dual structure buried rail may reduce buried rail resistance which may reduce voltage drop thereacross and provide for improved semiconductor device and/or active device region performance. The dual structure buried rail may provide power potential delivery, provide potential sinking, or the like, to one or more active device region(s).

Dual structured buried rail

A skip-level through-silicon via structure is provided that enables low resistance via connection for backside power distribution by skipping one or more intermediate backside metal layers. The skip-level through-silicon via structure can enable a greater design flexibility for power grid. The skip-level through-silicon via structure has a large size that provides lower through-silicon via resistance as compared with conventional through-silicon via structures.

Skip-level TSV with hybrid dielectric scheme for backside power delivery

A semiconductor device includes a field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extend vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region includes a conduit liner and an inner column internal to the conduit liner that extends below a bottom surface of the wraparound gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.

Field effect transistor with backside source/drain

A semiconductor device includes a backside power rail, a backside ground rail, and a backside isolation rail between the backside power rail and the backside ground rail. The backside isolation rail may provide adequate electrical isolation between the backside power rail and the backside ground rail, thereby enabling the backside power rail and the backside ground rail to be located relatively near to one another. The backside isolation rail may also cure actual electrical shorts between the backside power rail and the backside ground rail.

Isolation rail between backside power rails

Growing community of inventors

Lagrangeville, NY, United States of America

Lawrence Alfred Clevenger