International Business Machines Corporation

Stmicroelectronics Gmbh

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Infineon Technologies Ag

Other

Globalfoundries Singapore Pte. Ltd.

Elpis Technologies Inc.

Adeia Semiconductor Solutions LLC

Samsung Electronics Co., Ltd.

Freescale Semiconductor,inc.

Chartered Semiconductor Manufacturing Ltd (corporation)

Kyndryl, Inc.

Tessera LLC

Internatoinal Business Machines Corporation

Lawrence Alfred Clevenger

Michael Rizzolo

Benjamin David Briggs

Carl John Radens

Chih-Chao Yang

Christopher J Penny

John H Zhang

Timothy Joseph Dalton

Louis L Hsu

Robert Russell Robison

Junli Wang

Baozhen Li

Brent A Anderson

Kangguo Cheng

Terry Allen Spooner

Kirk David Peterson

Kisik Choi

Hosadurga K Shobha

Theodorus E Standaert

Keith Kwong Hon Wong

Matthew Earl Colburn

Sivananda K Kanakasabapathy

Takashi Ando

Hsueh-Chung Chen

Cyril Cabral, Jr

Kevin Shawn Petrarca

Koichi Motoyama

Louis Lu-Chen Hsu

Yann Mignot

Ruilong Xie

Fee Li Lie

Joshua M Rubin

John Edward Sheets, Ii

Jonathan Hudson Connell, Ii

Nalini Kanta Ratha

Balasubramanian Pranatharthiharan

Takeshi Nogami

Satyanarayana Venkata Nitta

Zhenxing Bi

Zhengwen O Li

Dureseti Chidambarrao

Yuk Lung Chan

Elbert Emin Huang

Jack Allan Mandelman

Sampath Purushothaman

Ekmini Anuja De Silva

Qinghuang Lin

Wai-Kin Li

Richard Stephan Wise

Andrew Herbert Simon

Ronald G Filippi

Gregory J Boss

Huilong Zhu

Nicolas J Loubet

John Elbert Moore, Jr

Julien Frougier

Zheng Xu

Andrew R Jones

Charles Leon Arvin

Kevin Charles Mcconnell

Su Chen Fan

Marc Adam Bergendahl

Omer H Dokumaci

Griselda Bonilla

Xiao Hu Liu

Alain F Loiseau

Jeffrey P Gambino

Chen Zhang

Dechao Guo

Shom Ponoth

Ruqiang Bao

Timothy Dooling Sullivan

Kenneth Parker Rodbell

Arvind Kumar

Thomas M Shaw

Conal Eugene Murray

John Kenneth DeBrosse

Bruce Bennett Doris

Tenko Yamashita

Veeraraghavan S Basker

Chanro Park

Clement Hsingjen Wann

Oleg Gluschenkov

Hemanth Jagannathan

Mukta G Farooq

Soon-Cheon Seo

Katherine Lynn Saenger

Michael Patrick Chudzik

Laertis Economikos

Effendi Leobandung

Chung H Lam

Daniel C Edelstein

Yun Yu Wang

Lars W Liebmann

Terence B Hook

Christian Lavoie

Reinaldo Ariel Vega

Injo Ok

Chandrasekharan Kothandaraman

Robert C Wong

Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first power plane electrically connected to a first plurality of via-to-backside power planes (VBPPs), a second power plane, and a plurality of pass through vias electrically connecting the second power plane to a second plurality of VBPPs, wherein the plurality of pass through vias pass through the first power plane.

Backside power plane

A semiconductor device is provided. The semiconductor device includes a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions. The semiconductor device also includes a gate cut region at cell boundaries between the first and second S/D epitaxial regions, a dielectric liner and a dielectric core formed in the gate cut region, and a backside power rail (BPR) and a backside power distribution network (BSPDN). The semiconductor device also includes a power via passing through the dielectric core and connecting to the BPR and BSPDN, first metal contacts formed in contact with the first and second S/D epitaxial regions, and a via to backside power rail (VBPR) contact. The dielectric liner separates the power via from the first S/D epitaxial region.

Semiconductor device with power via

A top via interconnect with enlarged via top and a fabrication method therefor. One embodiment may comprise a semiconductor interconnect structure, comprising a first dielectric layer having a top surface, a bottom metal line formed in the dielectric layer, a second dielectric layer deposited above the top surface of the first dielectric layer, a via etched through the second dielectric layer above the bottom metal line, wherein the via exposes at least a portion of the top surface of the first dielectric layer, and a metal stud in the via that extends over the exposed at least a portion of the first dielectric layer. The metal stud in the via may further comprise a shoulder surface and a convex top surface.

TopVia interconnect with enlarged via top

A phase change memory (PCM) cell includes a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, and a phase change section positioned between the first electrode and the second electrode. The phase change section includes a first phase change material having a first resistance drift coefficient, and a second phase change material having a second resistance drift coefficient that is greater than the first resistance drift coefficient. An axis of the PCM cell extends between the first electrode and the second electrode, and the second phase change material is offset from the first phase change material in a direction that is perpendicular to the axis.

Composite material phase change memory cell

A method is presented for employing double-patterning to reduce via-to-via spacing. The method includes forming a mandrel layer over a substrate, forming sacrificial hardmask layers over the mandrel layer defining a litho stack, creating a pattern in the litho stack, the pattern having a narrow section connecting two wider sections to define a substantially hour-glass shape, depositing a spacer assuming a shape of the pattern, and etching the litho stack to expose the mandrel layer and metal lines, wherein the metals lines define sharp distal ends reducing a distance between the metal lines.

Metal lines with low via-to-via spacing

A VTFET is on a wafer and a backside power delivery network is on a backside of the wafer. A first backside contact is connected to a gate of the VTFET and a first portion of the backside power delivery network. The VTFET has a first width and the first width is a contacted poly pitch (CPP). The first backside contact may be at least the first width from the VTFET. The first backside contact may be double the first width from the VTFET.

Vertical-transport field-effect transistor with backside gate contact

A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.

Forming self-aligned vias and air-gaps in semiconductor fabrication

Embodiments of the invention include a first source region and a first drain region forming a first L-shaped layout. The first source and drain regions are formed on a bottom gate spacer material. Embodiments include a second source region and a second drain region forming a second L-shaped layout, the first L-shaped layout and the second L-shaped layout being interrupted by a gate. One of the first source and drain regions extends in a direction beyond the bottom gate spacer material to form the first L-shaped layout, wherein the direction is parallel to a lengthwise direction of the gate.

Stacked transistor layout for improved cell height scaling

A first metal layer is deposited on a substrate. The first metal layer is etched to form one or more metal lines and expose portions of the substrate. A second metal layer is deposited on the exposed portions of the substrate between the one or more metal lines. The first metal layer is patterned to form one or more vertical vias. A dielectric layer is deposited on the exposed portions of the substrate between an exposed sidewalls of the first metal layer and an exposed sidewalls of the second metal layer.

Advanced metal interconnect

A semiconductor interconnect structure comprises a substrate, a plurality of metal lines disposed relative to the substrate and a plurality of first and second caps disposed on the metal lines wherein the first caps comprise a first dielectric material and the second caps comprise a second dielectric material different from the first dielectric material.

Dielectric caps for power and signal line routing

Embodiments of the invention include vertically stacked field-effect transistors (FETs). The vertically stacked FETs include at least one first transistor and at least one second transistor separated by a dielectric isolation layer. Gate material is adjacent to the at least one first transistor and the at least one second transistor, at least one first height vertical layer being adjacent to and about a height of the gate material, at least one second height vertical layer being adjacent to and less than the height of the gate material.

Gate-cut and separation techniques for enabling independent gate control of stacked transistors

A semiconductor device includes a plurality of field effect transistors (FET) formed upon semiconductor fins. Each FET includes a gate disposed transversely upon a first portion of the fins of the FET, one or more source/drain regions disposed upon the fins and in contact with the gate, and an electrically isolating layer disposed adjacent to a second portion of the fins above the gate and the source/drain regions, the electrically isolating layer having an interface with the gate. The device further includes a buried power rail (BPR) disposed between otherwise adjacent FETs. The BPR includes a metal rail extending beyond the interface into the gate, and electrically isolating sidewalls separating the metal rail from the gate and the source/drain regions. The device also includes a via-buried power rail contact disposed adjacent to the electrically isolating sidewalls, in contact with the metal rail, and in contact with one source/drain region.

Semiconductor device having a backside power rail

A semiconductor structure comprising a substrate, a first metal layer on top of the substrate, a second metal layer on top of the first metal layer and a dielectric layer adjacent to the second metal layer and at least part of the first metal layer and on top of at least part of the first metal layer. The first metal layer includes a via. The width of the second metal layer is the same as the width of the via of the first metal layer.

Top via patterning using metal as hard mask and via conductor

Integrated chips include first lines, formed on an underlying substrate. Spacers are formed conformally on sidewalls of the plurality of lines. Etch stop remnants are positioned on the sidewalls of the plurality of lines, between the spacers and the underlying substrate. Second lines are formed on the underlying substrate, between respective pairs of adjacent first lines.

Single-mask alternating line deposition

A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.

Stacked transistors with different channel widths

Growing community of inventors

Lagrangeville, NY, United States of America

Lawrence Alfred Clevenger