International Business Machines Corporation

Stmicroelectronics Gmbh

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Infineon Technologies Ag

Other

Globalfoundries Singapore Pte. Ltd.

Elpis Technologies Inc.

Adeia Semiconductor Solutions LLC

Samsung Electronics Co., Ltd.

Freescale Semiconductor,inc.

Chartered Semiconductor Manufacturing Ltd (corporation)

Kyndryl, Inc.

Tessera LLC

Internatoinal Business Machines Corporation

Lawrence Alfred Clevenger

Michael Rizzolo

Benjamin David Briggs

Carl John Radens

Chih-Chao Yang

Christopher J Penny

Nicholas Anthony Lanzillo

John H Zhang

Timothy Joseph Dalton

Louis L Hsu

Brent A Anderson

Robert Russell Robison

Junli Wang

Baozhen Li

Kangguo Cheng

Terry Allen Spooner

Hosadurga K Shobha

Kisik Choi

Kirk David Peterson

Theodorus E Standaert

Keith Kwong Hon Wong

Matthew Earl Colburn

Sivananda K Kanakasabapathy

Takashi Ando

Hsueh-Chung Chen

Cyril Cabral, Jr

Kevin Shawn Petrarca

Koichi Motoyama

Ruilong Xie

Yann Mignot

Louis Lu-Chen Hsu

Fee Li Lie

Joshua M Rubin

John Edward Sheets, Ii

Jonathan Hudson Connell, Ii

Nalini Kanta Ratha

Balasubramanian Pranatharthiharan

Takeshi Nogami

Satyanarayana Venkata Nitta

Zhenxing Bi

Zhengwen O Li

Dureseti Chidambarrao

Yuk Lung Chan

Elbert Emin Huang

Jack Allan Mandelman

Sampath Purushothaman

Ekmini Anuja De Silva

Qinghuang Lin

Wai-Kin Li

Richard Stephan Wise

Su Chen Fan

Andrew Herbert Simon

Ronald G Filippi

Gregory J Boss

Huilong Zhu

Nicolas J Loubet

John Elbert Moore, Jr

Julien Frougier

Zheng Xu

Andrew R Jones

Charles Leon Arvin

Kevin Charles Mcconnell

Marc Adam Bergendahl

Omer H Dokumaci

Griselda Bonilla

Xiao Hu Liu

Jeffrey P Gambino

Chen Zhang

Dechao Guo

Shom Ponoth

Ruqiang Bao

Reinaldo Ariel Vega

Timothy Dooling Sullivan

Kenneth Parker Rodbell

Arvind Kumar

Thomas M Shaw

Conal Eugene Murray

Bruce Bennett Doris

Tenko Yamashita

Veeraraghavan S Basker

Chanro Park

Clement Hsingjen Wann

Oleg Gluschenkov

Hemanth Jagannathan

Mukta G Farooq

Soon-Cheon Seo

Katherine Lynn Saenger

Michael Patrick Chudzik

Laertis Economikos

Effendi Leobandung

Chung H Lam

Daniel C Edelstein

Shogo Mochizuki

Yun Yu Wang

Lars W Liebmann

Son Van Nguyen

Terence B Hook

Christian Lavoie

Injo Ok

Chandrasekharan Kothandaraman

A back side contact structure is provided that directly connects a first electrode of a MRAM, which is present in a back side of a wafer, to a source/drain structure of a transistor. The back side contact is self-aligned to the source/drain structure of the transistor as well as to the first electrode of the MRAM. The close proximity between the MRAM and the source/drain structure increases the speed of the device. MRAM yield is not compromised since no re-sputtering of back side contact metal onto the MRAM occurs.

MRAM integration with self-aligned direct back side contact

An IC memory device includes a substrate and an array of memory cells on the substrate. Each memory cell includes at least one memory cell transistor in a layer of the device adjacent to the substrate. In the same layer, the device also includes a plurality of shunt transistors. The device also includes a buried metal signal rail, which is disposed between the array of memory cells and the plurality of shunt transistors in a buried layer that is embedded into the substrate below the transistors. The device also includes single-layer vias, which are in same layer as the transistors and electrically connect the memory cell transistors to the shunt transistors through the buried metal signal rail.

Buried metal signal rail for memory arrays

A dual structure buried rail includes an upper rail and a lower rail. The upper rail may be inset relative to the lower rail. In other words, the lower rail may be wider than the upper rail, and/or the lower rail may have a larger geometrical volume than the upper rail. The upper rail may be located at a boundary of, and/or directly next to, an active device region and the lower rail may extend directly underneath at least a portion of the active device region. The lower rail may extend the entire length of the upper rail. The dual structure buried rail may reduce buried rail resistance which may reduce voltage drop thereacross and provide for improved semiconductor device and/or active device region performance. The dual structure buried rail may provide power potential delivery, provide potential sinking, or the like, to one or more active device region(s).

Dual structured buried rail

A skip-level through-silicon via structure is provided that enables low resistance via connection for backside power distribution by skipping one or more intermediate backside metal layers. The skip-level through-silicon via structure can enable a greater design flexibility for power grid. The skip-level through-silicon via structure has a large size that provides lower through-silicon via resistance as compared with conventional through-silicon via structures.

Skip-level TSV with hybrid dielectric scheme for backside power delivery

A semiconductor device includes a field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extend vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region includes a conduit liner and an inner column internal to the conduit liner that extends below a bottom surface of the wraparound gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.

Field effect transistor with backside source/drain

A semiconductor device includes a backside power rail, a backside ground rail, and a backside isolation rail between the backside power rail and the backside ground rail. The backside isolation rail may provide adequate electrical isolation between the backside power rail and the backside ground rail, thereby enabling the backside power rail and the backside ground rail to be located relatively near to one another. The backside isolation rail may also cure actual electrical shorts between the backside power rail and the backside ground rail.

Isolation rail between backside power rails

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a metal level, the metal level includes a metal strip including a notch at a side of the metal strip or a pass-through inside the metal strip, wherein the notch or the pass-through is at least partially filled with a dielectric material. The metal level further includes a conductive wiring that vertically passes through the metal strip. The conductive wiring is at least partially inside the notch or inside the pass-through and is insulated from the metal strip by the dielectric material. Methods of manufacturing the semiconductor structure are also provided.

Pass-through wiring in notched interconnect

Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first power plane electrically connected to a first plurality of via-to-backside power planes (VBPPs), a second power plane, and a plurality of pass through vias electrically connecting the second power plane to a second plurality of VBPPs, wherein the plurality of pass through vias pass through the first power plane.

Backside power plane

A semiconductor device is provided. The semiconductor device includes a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions. The semiconductor device also includes a gate cut region at cell boundaries between the first and second S/D epitaxial regions, a dielectric liner and a dielectric core formed in the gate cut region, and a backside power rail (BPR) and a backside power distribution network (BSPDN). The semiconductor device also includes a power via passing through the dielectric core and connecting to the BPR and BSPDN, first metal contacts formed in contact with the first and second S/D epitaxial regions, and a via to backside power rail (VBPR) contact. The dielectric liner separates the power via from the first S/D epitaxial region.

Semiconductor device with power via

A top via interconnect with enlarged via top and a fabrication method therefor. One embodiment may comprise a semiconductor interconnect structure, comprising a first dielectric layer having a top surface, a bottom metal line formed in the dielectric layer, a second dielectric layer deposited above the top surface of the first dielectric layer, a via etched through the second dielectric layer above the bottom metal line, wherein the via exposes at least a portion of the top surface of the first dielectric layer, and a metal stud in the via that extends over the exposed at least a portion of the first dielectric layer. The metal stud in the via may further comprise a shoulder surface and a convex top surface.

TopVia interconnect with enlarged via top

A phase change memory (PCM) cell includes a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, and a phase change section positioned between the first electrode and the second electrode. The phase change section includes a first phase change material having a first resistance drift coefficient, and a second phase change material having a second resistance drift coefficient that is greater than the first resistance drift coefficient. An axis of the PCM cell extends between the first electrode and the second electrode, and the second phase change material is offset from the first phase change material in a direction that is perpendicular to the axis.

Composite material phase change memory cell

A method is presented for employing double-patterning to reduce via-to-via spacing. The method includes forming a mandrel layer over a substrate, forming sacrificial hardmask layers over the mandrel layer defining a litho stack, creating a pattern in the litho stack, the pattern having a narrow section connecting two wider sections to define a substantially hour-glass shape, depositing a spacer assuming a shape of the pattern, and etching the litho stack to expose the mandrel layer and metal lines, wherein the metals lines define sharp distal ends reducing a distance between the metal lines.

Metal lines with low via-to-via spacing

A VTFET is on a wafer and a backside power delivery network is on a backside of the wafer. A first backside contact is connected to a gate of the VTFET and a first portion of the backside power delivery network. The VTFET has a first width and the first width is a contacted poly pitch (CPP). The first backside contact may be at least the first width from the VTFET. The first backside contact may be double the first width from the VTFET.

Vertical-transport field-effect transistor with backside gate contact

A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.

Forming self-aligned vias and air-gaps in semiconductor fabrication

Embodiments of the invention include a first source region and a first drain region forming a first L-shaped layout. The first source and drain regions are formed on a bottom gate spacer material. Embodiments include a second source region and a second drain region forming a second L-shaped layout, the first L-shaped layout and the second L-shaped layout being interrupted by a gate. One of the first source and drain regions extends in a direction beyond the bottom gate spacer material to form the first L-shaped layout, wherein the direction is parallel to a lengthwise direction of the gate.

Stacked transistor layout for improved cell height scaling

Growing community of inventors

Lagrangeville, NY, United States of America

Lawrence Alfred Clevenger