American Telephone and Telegraph, Co.

American Telephone and Telegraph Company; At&t Information Systems

Lawrence A Welsch

Thomas P Bishop

Mark H Davis

Grover T Surratt

David N Horn

Processors (101) of a multiprocessor system (FIG. 1) communicate across bus (150) via a low-latency packet protocol featuring per-logical channel input queues (143) and output queues (144), different per-processor priorities for sending data packets (FIG. 10) and data packet-acknowledging 'quick' messages (FIG. 11), and separate buffers (923; 918) for receiving data packets and 'quick' messages, respectively. Transmitted data packets afflicted by error, receive buffer overflow, and input queue-full conditions are discarded by the receiving processor and are retransmitted by the sending processor.

Inter-processor communication protocol

In a multiprocessor system, processors are connected to an interconnecting bus by means of bus interface circuits which comprise an address buffer in addition to data buffers. The interconnecting bus, in addition to a destination address and data also carries an originating address identifying the processor transmitting the data. In the event of a receive buffer overload condition in the receiving bus interface circuit, a negative acknowledge signal is transmitted on the bus and the originating address is queued in the address buffer. When the buffer overflow condition has been relieved, a retransmission request is sent to the first processor identified in the address buffer and its message is received. This procedure will be repeated for each processor identified in the address buffer.

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Naperville, IL, United States of America

Lawrence A Welsch