Rca Inc.

Sarnoff Corporation

General Electric Company

Sri International

Lawrence A Goodman

Alvin M Goodman

Lawrence K White

James W Tuska

Gary M Dolny

Kenneth Warren Hang

Ashok Narayan Prabhu

Leslie Ronald Avery

Grzegorz Kaganowicz

David E Carlson

Joseph J Hanak

Aaron W Levine

Robert Amantea

Ronald N Friel

John P Russell

Harry Louis Pinch

Vipulkumar K Patel

Dietrich Meyerhofer

Paul H Robinson

Ronald Keith Smeltzer

William Bernard Hall

Thomas Stephen Villani

Herman F Gossenberger

Kenneth P Smith

A method for fabricating a back-illuminated semiconductor imaging device on an ultra-thin semiconductor-on-insulator wafer (UTSOI) is disclosed. The UTSOI wafer includes a mechanical substrate, an insulator layer, and a seed layer. At least one dopant is applied to the semiconductor substrate. A first portion of an epitaxial layer is grown on the seed layer. A predefined concentration of carbon impurities is introduced into the first portion of the epitaxial layer. A remaining portion of the epitaxial layer is grown. During the epitaxial growth process, the at least one dopant diffuses into the epitaxial layer such that, at completion of the growing of the epitaxial layer, there exists a net dopant concentration profile which has an initial maximum value at an interface between the seed layer and the insulator layer and which decreases monotonically with increasing distance from the interface within at least a portion of at least one of the semiconductor substrate and the epitaxial layer.

High-efficiency thinned imager with reduced boron updiffusion

A method of adjusting the position of a micro-mechanical bi-material cantilever is provided. The bi-material includes a first and a second material and each material has a corresponding thermal expansion coefficient. The method includes implanting ions predominantly into one material of the bi-material to modify internal stress in one of the first and second materials relative to the other material. The deformation of the bi-material is then detected to modulate the implantation of ions thereto.

Method for reducing variations in arrays of micro-machined cantilever structures using ion implantation

An integrated circuit system includes a substrate of an electrical insulating material having a surface. Mounted on the surface of the substrate is an IC, a semiconductor piece having therein a circuit, such as a microprocessor, having a plurality of functional blocks. Also mounted on the substrate are a plurality of power supply chips. Each of the power supply chips is connected through conductors and vias in the substrate to a separate functional block on the IC semiconductor piece. Each of the power supply chips forms part of a circuit, such as a DC-DC converter, which is capable of reducing a voltage supplied thereto to a lower voltage suitable for the particular functional block to which the particular power supply chip is connected. Thus, a single relatively large voltage fed to the power supply chips through conductors on the substrate is reduced by each power supply chip to a lower voltage suitable for the particular functional block of the IC semiconductor piece.

Integrated circuit power supply

A method of making a liquid crystal display which has a layer of polysilicon on a surface of a substrate, a gate of a conductive material over and insulated from a portion of the polysilicon layer, a layer of an insulating material over the gate, and a metal layer on the insulating layer. The method includes forming a layer of an insulating material over the metal layer and then subjecting the device to a plasma containing hydrogen to diffuse the hydrogen through the insulating layers and the metal layer into the polysilicon layer.

Hydrogenation of polysilicon thin film transistors

A power supply integrated module includes a metal substrate having a surface and a body of a dielectric material, such as a glass or ceramic, mounted on and bonded to the surface of the substrate. The body is formed of a plurality of layers of the dielectric material bonded together. Areas of a conductive material and a resistive material are coated on the surfaces of the layers of the body to form passive electronic components, such as capacitors, resistors and inductors. At least one transformer is on or in the body. The transformer and passive electronic components are electrically connected by conductive interconnects on the layers of the body and vias of a conductive material extending through the layers of the body to form a power supply integrated circuit. Active electronic components, such as diodes and transistors, may also be mounted on the body and electrically connected in the power supply circuit.

Miniature power supply

A method of etching an opening having tapered wall in a layer of silicon carbide (SiC) includes forming a layer of a resist on the SiC layer. An opening having tapered wall is formed in the resist layer so as to expose a portion of the SiC layer. The exposed portion of the SiC layer is then exposed to a plasma of a gas containing carbon and fluorine to etch an opening through the SiC layer with the opening having tapered walls. If a layer of a glass is provided under the SiC layer, the plasma will also etch through the glass layer to provide an opening in the glass layer having tapered walls.

Patterning silicon carbide films

A circuit in accordance with the invention has a complementary pair of a MISFET and a COMFET with their drains connected together. This allows fabrication on a single substrate for greater reliability and reduced cost. The circuit can be used in a full or one half 'H-bridge' configuration for controlling current through a load such as a motor.

Complementary circuit and structure with common substrate

A vertical MOSFET device includes a semiconductor wafer having source, body and drain regions of alternate conductivity type disposed therein. The source and drain regions are located so as to define the length and width of a channel region in the body region at a surface of the wafer. The body region further includes a similar conductivity type supplementary region having a relatively high areal dopant concentration. The supplementary region, which can be fabricated by ion implantation, extends laterally beneath a portion of the channel region. A source electrode is disposed on one wafer surface and a drain electrode is disposed on an opposing wafer surface.

Vertical MOSFET with reduced bipolar effects

A vertical MOSFET in a silicon wafer having opposing major surfaces includes a source electrode on one surface, a drain electrode on the second surface, and an internally disposed insulated gate. The silicon between the insulated gate and each of the major surfaces is of first conductivity type and the silicon that is laterally adjacent to the insulated gate is of second conductivity type, such that a predetermined voltage on the insulated gate creates an inversion channel extending a predetermined distance into the laterally adjacent silicon. That portion of the laterally adjacent silicon where the inversion channel is formed is of relatively lightly doped material, whereas other areas of the laterally adjacent silicon is relatively heavily doped. The silicon that is between the insulated gate and each wafer surface includes a relatively lightly doped voltage-supporting region contiguous with the insulated gate and the laterally adjacent silicon and a relatively heavily doped region between this voltage-supporting region and the surface. Additionally, the interface between the insulated gate and the laterally adjacent silicon has a low density of interface states.

Method for fabricating bidirectional vertical power MOS device

A method for decreasing the turnoff time in a crystalline semiconductor region within a semiconductor device comprises initially providing a semiconductor region having a predetermined density of pinning centers. The semiconductor region is then irradiated so as to yield crystal damage that is equivalent to or greater than that which would be produced by irradiating with 1 MeV neutrons at a fluence greater than approximately 10.sup.13 cm.sup.-2. The region is then annealed at a temperature of approximately 350.degree. to 450.degree. C. for approximately 15 minutes to one hour so as to yield a density of stable recombination centers correlating with the pinning centers that provides a stable minority carrier lifetime within the semiconductor region.

Method for increasing the switching speed of a semiconductor device by

Bidirectional vertical power MOS device and fabrication method

A method for revealing the presence of heavy metal impurities that may have been introduced during the formation of a layer, such as the deposition of an epitaxial layer on a semiconductor substrate, uses the constant-magnitude steady-state surface photovoltage (SPV) method for determining the minority-carrier diffusion length by essentially two determination steps. A large ratio of the respective diffusion lengths determined before (actually measured or based on a priori knowledge of similar material) and after the epitaxial deposition step is indicative of the presence of a heavy metal impurity in the epitaxial layer. The method is based on the fact that the contaminating metal distributes itself substantially uniformly not only through the epitaxial layer but also throughout the substrate.

Method using surface photovoltage (SPV) measurements for revealing heavy

Method for making vertical MOSFET with reduced bipolar effects

A MOSFET device having minimized parasitic bipolar effects comprises a substrate having a surface at which source and drain regions are spaced so as to define a channel portion in a body region. The channel portion is formed in a relatively low conductivity portion of the body region, the remainder of the body region being of higher conductivity. A gate overlies the channel portion, and a method for automatically aligning the gate to a grooved MOSFET is described.

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Plainsboro, NJ, United States of America

Lawrence A Goodman