Digital Equipment Corporation

Lawrence A Chisvin

Donald W Smelser

John K Grooms

Richard Lee Sites

David W Hartwell

Joseph F Rantala

James C Stegeman

Gregg Bouchard

Methodology and circuitry for managing read and write commands from nodes to a shared memory resource on a common data bus, including nodes with write-back caches, nodes with write-through caches and nodes without caches.

Memory subsystem command input queue having status locations for

A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroninstruction pipelining is employed (instead of microinstruction pipelining), with queuing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. A hierarchical cache arrangement is used, increasing the likelihood of a cache hit. A writeback cache is used (instead of writethrough) and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. Separate queues are provided for the return data from memory and cache invalidates, yet the order or bus transactions is maintained by a pointer arrangement. The bus protocol used by the CPU to communicate with the system bus is of the pended type, with transactions on the bus identified by an ID field specifying the originator, and arbitration for bus grant goes one simultaneously with address/data transactions on the bus.

Combined queue for invalidates and return data in multiprocessor system

A method and apparatus for implementing a capture of a long contiguous chain of data bus cycles for the memory system of a data processing system with memory units that alternate between real time capture of segments of the chain of data bus cycles and processing of the data bus signals in the captured segments.

Method and apparatus for capturing real-time data bus cycles in a data

A method and apparatus for error detection is disclosed. A data word and its check bits are read from memory, and new check bits are generated form the data word read. A logical operation is performed between the new check bits and the check bits read from memory to generate a syndrome. The syndrome is decoded to detect the presence or absence of an uncorrectable error. If an uncorrectable error is detected, a logical operation is performed between the new check bits and a byte write error code to generate a third set of check bits, which are then written into memory along with the data word.

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Sudbury, MA, United States of America

Lawrence A Chisvin