Texas Instruments Corporation

Laurinda W Ng

Byron Lovell Williams

Jose L Melendez

Darius Lammont Crenshaw

Alec James Morton

Lawrence D Dyer

Michael A Mignardi

Robert G McKenna

C Matthew Thompson

Betty S Mercer

Erika Leigh Shoemaker

Bryon L Williams

Ronald S Croff

The present invention provides an interconnect for use in an integrated circuit, a method for manufacturing the interconnect, and a method for manufacturing an integrated circuit including the interconnect. The interconnect (), among other elements, includes a surface conductive lead () located in an opening formed within a protective overcoat (), and a barrier layer () located between the protective overcoat () and the surface conductive lead (), a portion of the barrier layer () forming a skirt () that extends outside a footprint of the surface conductive lead ().

Method for manufacturing an interconnect

The present invention includes an integrated circuit switch including a membrane supported over a first conductor on a substrate, a conductive region on the membrane and connecting to the first conductor on the substrate, a pulldown electrode on the substrate and under the membrane and a pillar to support the membrane after the pulldown threshold has been reached. A voltage greater than a pulldown threshold is applied between the membrane and the pulldown electrode will pull the membrane down to make a capacitive coupling to the first conductor. The addition of the pillars increases the upward restoring force when the activation voltage is removed.

Mechanically assisted restoring force support for micromachined membranes

A method of separating wafers, such as those used for semiconductor device manufacture, into die. A partly fabricated wafer is covered with a protective coating over its top surface (10). The wafer is then inscribed to define separation lines between die, with the separation lines being of a predetermined depth (12). The protective coating is then removed (14), and at least one processing step is performed at the wafer level (15, 22-24), before the inscribed wafer is separated into die. Then, the wafer is separated into die along the separation lines (17).

Separation of wafer into die with wafer-level processing

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Plano, TX, United States of America

Laurinda W Ng