Itt Industries, Inc.

Deutsche Itt Industries Gmbh

Laurin C Freyberger

Friedrich Schmidtpott

Hermannus Schat

Daniel Mlynek

Peter M Flamm

Manfred F Ullrich

Ljubomir Micic

Bernd Novotny

Wolfgang Sauer

Hermanus Schat

In a chroma control circuit for a digital television receiver, the system clock lies in the range of four-times the chrominance-subcarrier frequency. The originally received color-burst signal is locked in frequency and phase to the system clock by means of an all-digital phase-locked loop. The phase-difference angle between the color-burst signal and the system clock appears as a sine or cosine value in the two standard color-difference signals of the chrominance demodulator during the reception of the color-burst signal. One of the standard color-difference signals, the B-Y signal, is fed through a horizontal-frequency-suppressing loop filter to a digital oscillator. The latter determines the speed of rotation of a hue adjustment angle rotating at approximately constant angular speed. The respective sine and cosine values of the hue adjustment angle are read as data values from first and second read-only memories, respectively, and are fed to the sine and cosine inputs of a hue adjuster in a calculating stage which derives the color-burst signal and the chrominance signal.

Chroma control circuit for a digital television receiver

A phase-locked loop for the color subcarrier signal in a television receiver is opened for non-sychronizable signals and the voltage controlled oscillator oscillates on a predetermined frequency. The lock in characteristic of the phase-locked loop is thereby improved.

Color-television receiver with at least one integrated circuit for

The burst signal existing on the back porch of the composite color signal is brought to a predetermined normalized value with the aid of an amplitude control loop. In order to further increase the gain of a multiplier provided for in the control loop the multiplier is preceded by a premultiplier of simple design, whose multiplication factor is capable of being switched over in powers of two. A multiplication factor setting signal, is converted via a code converter into two control signals, with the first control signal setting the multiplication factor of the premultiplier, and with the second control signal setting the multiplication factor of the multiplier.

Integrated digital gain control circuit for digital chrominance signals

In this IC set, the dark currents and the white levels of the three electron guns, the leakage currents of the cathodes, and a light-detector current are measured during four successive vertical blanking intervals. The cathode leakage currents and the dark currents are measured in the first half of the vertical blanking interval, and the light-detector current and the white-level currents are measured at the end of this interval. From these measured data and alignment data stored in a reprogrammable memory (ps), a microprocessor (mp) contained together with the memory (ps) in an integrated circuit (ic2) derives operating data for the picture tube (b) as well as further data. These operating data are transferred over a wire of a chroma bus (cb), over which chroma signals are transferred during the vertical sweep, into a shift register (sr) of a further integrated circuit (ic3) at the beginning of each vertical blanking interval, from where they are passed on to the picture tube (b) in groups via digital-to-analog converters and analog amplifiers. By the use of the chroma bus for a dual purpose, and the successive measurements of the above-mentioned picture-tube data, a saving of external terminals of the integrated circuits (ic1, ic2, ic3) is achieved.

Set of three integrated circuits for digital video signal processing in

In a television receiver, a circuit is provided which automatically controls the focus voltage of the picture tube. The circuit uses a sensor to obtain focusing information from the picture tube wherein this information is processed by an alignment computer and a digital to analog converter which controls a blocking oscillator circuit to provide a focusing voltage.

Television receiver with an automatic digital alignment system

Digital color signal processing circuitry includes a multiplier which multiplies two demodulated digital color-difference signals by a digital color-saturation signal to provide three time-division-multiplexed signal pairs, each of which is added to the digital luminance signal by an adder. The color-saturation-signal input of the multiplier is preceded by a second multiplier to which the color-saturation signal and multiplier factors stored in a memory (sp) are applied. These multiplier factors are permanently stored by the manufacture of the color-television receiver or can be varied or adjusted during the operation of the receiver. The three adders are followed by three digital-to-analog converters which provide the analog color signals.

Digital signal processing circuitry for a color-television receiver

An improved kit of two integrated circuits having a phase-locked loop clock oscillator for use in a color television receiver utilizing digital signal processing is described. The voltage controlled oscillator and the phase discriminator of the phase-locked loop are each located in a different one of the two integrated circuits. The control signals for the voltage controlled oscillator are transferred into it via a two-wire digital bus. External discrete components are eliminated.

Integrated circuit kit with a phase-locked loop for color television

In this IC set, the dark currents and the white levels of the three electron guns, the leakage currents of the cathodes, and a light-detector current are measured during four successive vertical blanking intervals. The cathode leakage currents and the dark currents are measured in the first half of the vertical blanking interval, and the light-detector current and the white level currents are measured at the end of this interval. From these measured data and alignment data stored in a reprogrammable memory (ps), a microprocessor (mp) contained together with the memory (ps) in an integrated circuit (ic2) derives operating data for the picture tube (b) as well as further data. These operating data are transferred over a wire of a chroma bus (cb), over which chroma signals are transferred during the vertical sweep, into a shift register (sr) of a further integrated circuit (ic3) at the beginning of each vertical blanking interval, from where they are passed on to the picture tube (b) in groups via digital-to-analog converters and analog amplifiers. By the use of the chroma bus for a dual purpose, and the successive measurements of the above-mentioned picture-tube data, a saving of external terminals of the integrated circuits (ic1, ic2, ic3) is achieved.

The interface circuit contains a single operational amplifier (OR, OG, OB) per chrominance channel, with a resistance network (WR, WG, WB) for white-level adjustment connected between the inverting input and the output of this amplifier. The output resistances of the matrix output amplifiers (MR, MG, MB) must be low, and a low-value resistor (RR, RG, RB) is connected between the output of each output amplifier and the noninverting input of each operational amplifier (OR, OG, OB). Video-signal, brightness-, blanking, and external-signal-control currents (ISR, ISG, ISB; IHR, IHG, IHB; IBR, IBG, IBB; IER, IEG, IEB) are applied to the non-inverting input of the respective operational amplifier. The control currents permit the white-level adjustment and the blanking-voltage adjustment to be made independently of each other and eliminate any interaction between brightness adjustment, blanking, and external-signal gating. Compared with prior art arrangements, a simpler circuit is obtained.

Integrated interface circuit between the RGB matrix and the video output

A deflection circuit is disclosed wherein squarewave clock pulses are applied to the input of an n-stage shift register, the series input of which is connected to a fixed potential, the decoder is a summing circuit having n inputs each of which is connected to a respective output of the n-stages of the shift register, the resetting input of the shift register is controlled by the last shift register stage and a deflecting means is controlled by a sawtooth signal resulting at the output of the summing circuit.

Deflection circuit for cathode-ray tubes

This relates to apparatus for the 'picture on picture' or 'program check' project. Storage, storage control circuits and clock signal generators are disclosed. The storage consists of two parts which are simultaneously fed by selected lines of the second program.

Television receiver equipped for simultaneously showing several programs

Several solutions to the problem of making integrable the known so-called tangent correction circuit of TV receivers are provided. The solutions are: a diode-resistor matrix, a voltage-dependent resistor arrangement or a regulating circuit.

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Bahlingen, Germany

Laurin C Freyberger