Minima Processor Oy

Aalto University Foundation

Lauri Koskinen

Matthew Turnquist

Jani Mäkipää

Navneet Gupta

Markus Hiienkari

Erkka Laulainen

Ari Paasio

Samuli Tuoriniemi

Risto Anttila

Tuomas Hollman

Jesse Simonsson

Jani MÄKIPÄÄ

The excitation of processing paths in a microelectronic circuit is organized by providing one or more pieces of input information to a decision-making software, and executing the decision-making software to decide, whether one or more of said processing paths of the microelectronic circuit are to be excited with test signals. Deciding that said processing paths are to be excited with said test signals results in proceeding to excite said one or more of said processing paths with said test signals and monitoring whether timing events occur on such one or more excited processing paths. A timing event is a change in a digital value at an input of a respective register circuit on an excited processing path, which change took place later than an allowable time limit defined by a triggering signal to said respective register circuit.

Method, arrangement, and computer program product for organizing the excitation of processing paths for testing a microelectric circuit

The performance of a microelectronic circuit can be configured by making an operating parameter assume an operating parameter value. An operating method comprises selectively setting the microelectronic circuit into a test mode that differs from a normal operating mode of the microelectronic circuit, and utilizing said test mode to input test input signals consisting of test input values into one or more adaptive processing paths within the microelectronic circuit. An adaptive processing path comprises processing logic and register circuits configured to produce output values from input values input to them. The performance of such an adaptive processing path can be configured by making an operating parameter assume an operating parameter value. The method comprises making said one or more adaptive processing paths form test output values on the basis of the respective test input values input to them, and forming a set of test output signals by collecting said test output values given by said one or more adaptive processing paths. The method comprises examining said set of test output signals, and forming a test result on the basis of said examining, and using said test result to select and set an operating parameter value for said operating parameter.

Applications of adaptive microelectronic circuits that are designed for testability

A controllable voltage source () is coupled to a microelectronic circuit () for providing an operating voltage. Said microelectronic circuit () is adaptive, so its performance is at least partly configurable by value of said operating voltage. The operating voltage is regulated into conformity with a target value. Reregulating said operating voltage into conformity with a new target value involves a time constant. On a processing path a first register circuit () comprises a data input coupled to an output of a preceding first logic unit (). The microelectronic circuit () responds to a digital value at said data input changing later than an allowable time limit by generating a timing event observation (TEO) signal. The allowable time limit is defined by at least one triggering edge of at least one triggering signal coupled to the first register circuit (). The system uses said TEO signal to trigger an increase in said operating voltage faster than said time constant.

System with microelectronic circuit, and a method for controlling the operation of a microelectronic circuit

A monitor circuit () for monitoring changes in an input digital value of a register circuit comprises a data input () configured to receive a copy of the input digital value of said register circuit, and one or more triggering signal inputs () configured to receive one or more triggering signals. One or more triggering edges thereof define an allowable time limit before which a digital value must appear at a data input of said register circuit to become properly stored in said register circuit. The monitor circuit comprises a data event (DE) output (), so that said monitor circuit is configured to produce a DE signal at said DE output () in response to a digital value at said data input () changing within a time window defined by said one or more triggering signals.

Register circuit with detection of data events, and method for detecting data events in a register circuit

A level shifter comprises a first control switch () for connecting an output terminal to a first supply voltage (VDDH) to set an output signal to be high, and a second control switch () for connecting the output terminal to a signal ground (GND) to set the output signal to be low. The level shifter comprises a pre-charging switch () for connecting the output terminal to the first supply voltage, and an input gate circuit () for controlling an ability of an input signal to control the second control switch. The level shifter comprises a keeper circuit () for controlling the first control switch based on the output signal. The first control switch is controlled with the first supply voltage when the output signal is low, and with a second supply voltage that is between the first supply voltage and the signal ground when the output signal is high.

Level shifter and a method for shifting voltage level

A control system for controlling an operating voltage of an electronic device is presented. The electronic device includes a timing event detector responsive to timing events, such as errors, related to operation of the electronic device. The control system includes a controller for decreasing the operating voltage when the rate of timing events is below a target level and for increasing the operating voltage when the rate of timing events exceeds the target level to search for a threshold voltage that is the smallest operating voltage at which the rate of timing events is substantially at the target level. The control system further includes a controllable clock signal generator for producing a clock signal for operating the electronic device so that the clock frequency is according to an increasing function of the operating voltage. Thus, it is possible to find a voltage-frequency operating point where the energy consumption is minimized.

System and a method for controlling operating voltage

There is provided an apparatus comprising thresholding means adapted to check if an average frequency of occurrence of timing violations is outside a range; and controlling means adapted to control at least one of a clock frequency, a processing, a heat generation, a bias voltage, a current, and a temperature in a direction to bring the average frequency of occurrence of timing violations into the range if the average frequency of occurrence of timing violations is outside the range.

Control mechanism based on timing information

A field effect transistor current mode differential logic circuit comprising load transistors for converting the current output of each differential leg current to voltage output, and means for configuring the bulk of each differential leg's load transistor to be connected to the drain of the load transistor for use the logic circuit in Subthreshold Source Coupled Logic (STSCL) mode, and means for configuring the bulk of each leg load transistor to be connected to a voltage or to source of the same transistor for use in MOS current more logic (MCML) operation.

Field effect transistor current mode logic with changeable bulk configuration of load transistors

An apparatus, comprising a clock adapted to provide a clock signal alternating with a cycle between a first level and a second level if a timing violation is not detected; a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level; a second combinational logic adapted to output a second signal based on the first signal passed through the first latch; a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means adapted to detect the timing violation of at least one of the first signal and of the second signal; a time stretching means adapted to stretch, if the timing violation is detected, the clock such that the clock alternates between the first level and the second level with a delay.

Preventing timing violations

A sequential circuit with transition error detector including a sequential element with an input that is asserted to the output during the second clock phase of a two phase clock signal, a transition error detector coupled to the sequential element input to assert an error signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase, wherein a transition error detection circuit comprises a current mode circuit as a detection circuit for transition timing error detection from signals derived from the sequential element clock signal and input signals.

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Helsinki, Finland

Lauri Koskinen