Sgs-thomson Microelectronics S.a.

Stmicroelectronics S.a.

Stmicroelectronics S.r.l.

France Telecom

Thomson Composants Militaires & Spaciaux

Laurent Sourgen

Mathieu Pierre Lisart

Sylvie Wuidart

Richard P Fournel

Serge Fruhauf

Rodolphe Uhlmann

Federico Pio

Jean Devin

Alain C Pomet

Nicola Zatelli

Bernard Plessier

Eric Depret

Gilles Lisimaque

Gilles Limisaque

In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.

Electronic device with encryption/decryption cells

An EEPROM cell is described as having a screening metal structure formed of preference in the first metal layer and located in substantial overlaying relationship at the floating gate terminal. This defeats the possibility of anomalous readings being obtained by measuring the amount of charge on the floating gate terminal. An additional screening metal structure, to be formed in the third and following metal layers, may be provided to fully overlie the cell and provide additional protection against anomalous readings.

Screened EEPROM cell

The access to memory words of an integrated circuit is protected by the creation of a decision table that receives addresses of instruction words and/or data words to be protected and that receives also addresses of the control bits of a control word assigned to a word to be protected. It can be shown that this mode of action provides greater security through the use of a decision table made in wired circuit form as well as greater flexibility through the programmable quality of the control words assigned to each memory word to be controlled.

Device for the protection of the access to memory words

A method for detecting the presence of a passivation layer on an integrated circuit comprises sending out a train of pulses of different widths at one end of a line of metal that winds on the surface of the integrated circuit beneath the protection layer of the integrated circuit. The line of metal and the dielectric layer of the integrated circuit form an RC filter. The number of pulses received at the other end of the line of metal is counted and compared with at least one characteristic reference value of the filter.

Method for the detection of the presence of passivation in an integrated

To form a ramp signal for the programming of a memory cell without losing excess voltage in a control circuit, the output of a voltage pull-up circuit is connected to the programming input using a P type transistor. It is shown that this P type transistor then charges the memory array at constant current, prompting a linear increase of the voltage. This results in preventing the memory cell that is to be programmed from being subjected to excessively sudden variations of voltage. It is shown that by acting in this way, the integrated circuit can be made to work even with very low voltages.

Circuit for the production of a programming high voltage

The present invention concerns a method for the numerical scrambling by permutation of data bits in a programmable circuit comprising a control unit and at least one data bus (DBUS) to transmit data between the control unit and several memory circuits. It consists of having data on the bus either in a scrambled form or in an unscrambled form according to whether it is instructions data or not. And data in some of the memories is scrambled. The present invention also concerns a method for realising a permutation circuit.

Method for numerically scrambling data and its application to a

The present invention concerns a method for protecting a write operation of a memory cell within an integrated circuit that comprises the introduction of a random period (d1) between the reception of an external write command and the application of a physical variable to the memory cell so as to thwart the determination of the applied waveform characteristics as a function of time of this physical variable. The present invention also concerns an integrated circuit that comprises a memory whose write operation is protected according to this method. An application of the present invention is in the domain of chip carrying cards, i.e. smartcard applications.

Protected writing method for an integrated memory circuit and a

A supply-voltage-monitoring circuit, for low-power integrated circuits, in which charge-sharing through a switched-capacitor chain is used to couple the supply voltage to a dynamic sensing node. The dynamic sensing node drives a half-latch, which is stable in a no-alarm condition.

Voltage threshold detection circuit with very low consumption

A decision circuit receives input addresses of instructions to be executed and data addresses to which the instructions have to be applied. The decision circuit either allows the execution of the instruction or prohibits the execution of the instruction if the instruction leads to a false operation or to a fraudulent attempt to divulge the system contents. A buffer register stores the instruction addresses and subsequently presents them to the decision circuit simultaneously with the data addresses. This device applies particularly to the protection of electronic integrated circuit memory cards.

Device for protecting memory areas of an electronic microprocessor

A supply-voltage-monitoring circuit, for low-power integrated circuits, in which charge-sharing through a switched-capacitor chain is used to couple the supply voltage to a dynamic sensing node. The dynamic sensing node drives a half-latch, which is stable in a no-alarm condition. In this circuit, the state of the output gets switched over in the first phase if the voltage at the terminals of the capacitor at the start of this stage (this voltage being equal to a fraction of the input voltage) crosses a determined threshold. This threshold is determined as a function of technical parameters for the construction of the circuit. These technical parameters are chiefly the threshold voltage of the transistor and the characteristics of the transistors that form the locking circuit.

Voltage threshold detection circuit with very low power consumption

In a memory, a zone descriptor contains authorizations to act which may pertain to actions of reading, writing and erasure and which concerns memory words of a zone of the memory controlled by this descriptor. The zone descriptor also has an information element indicating the length of the memory zone by including the address of the next descriptor. An internal zone control signal is produced in order to store a mode of management of the memory zone and, an address corresponding to the end of the zone. The end of zone address is then compared with the addresses delivered by an address counter. A modification of the stored information is prompted when the end of a zone is reached.

Circuit for the management of memory words

A decision circuit receives input addresses of instructions to be executed and data addresses to which the instructions are to be applied. The decision circuit either allows the execution of the instruction or prohibits the execution of the instruction if the instruction leads to a false operation or to a fraudulent attempt to divulge the system contents. A buffer register stores the instruction addresses and subsequently presents them to the decision circuit simultaneously with the data addresses. This device applies particularly to the protection of electronic integrated circuit memory cards.

Device for enabling the use of the contents of memory areas of an

An integrated circuit for a passive unit counting memory card comprises p levels (10, 11, 12) of data counting memory. The levels contain corresponding numbers of cases n.sub.1 . . . n.sub.p, a write operation being achieved in a case of an upper rank level each time all the cases of the lower rank level have been enabled, the cases of the lower levels then being erased. The circuit comprises p-1 ghost levels (21, 22) identical to the p-1 upper rank levels of the p counting levels. The addressing logic of the ghost levels is such that the cases of ghost levels are addressed in write phase simultaneously with the cases of the corresponding counting levels and, after a write phase, are addressed in erase phase simultaneously with the cases of the levels of lower rank than the one that has just been enabled.

Data counting memory card and reader

In order to modify the configuration of an integrated circuit, for example to restrict access by the user to certain functions or certain pieces of data of the circuit, the integrated circuit is provided with a first electronic lock capable of being locked or unlocked during a stage for the testing of the integrated circuit and capable of being irreversibly locked after the end of the testing stage, and a second electronic lock capable of being unlocked only so long as the first lock is unlocked. In this way, the entire circuit can be tested in the form in which it is presented to the user, the locking of the locks being, so to speak, simulated during the test.

Security locks for integrated circuit

A MOS fuse with programmable tunnel oxide breakdown is made up of a tunnel oxide EEPROM cell, which can be programmed/erased by a programming/erasure voltage having a slow-rising edge, while the tunnel oxide can be subjected to breakdown, when desired, by switching over to a programming/erasure voltage having a steep edge. Such fuse can be used in all MOS integrated circuits and particularly in memory card type applications.

Growing community of inventors

Aix en Provence, France

Laurent Sourgen