Vlsi Technology, Inc.

Nxp B.v.

Koninklijke Philips Corporation N.V.

Laurent Souef

Jerome Bombal

Bernard Ginetti

Patrick Da Silva

Philippe Gaglione

John Whittle

Didier Gayraud

A method of testing an integrated circuit, comprises providing a test vector to a shift register arrangement by providing test vector bits in series into the shift register arrangement () timed with a first, scan, clock signal (). The test vector bits are passed between adjacent portions of the shift register arrangement timed with the first clock signal () and an output response of the integrated circuit to the test vector is provided and analyzed. The output response of the integrated circuit to the test vector is provided under the control of a second clock signal () which is slower than the first clock signal. This testing method speeds up the process by increasing the speed of shifting test vectors and results into and out of the shift register, but without comprising the stability of the testing process. Furthermore, the method can be implemented without requiring additional complexity of the testing circuitry to be integrated onto the circuit substrate.

Scan testing methods

The invention relates to a testable integrated circuit. In order to replace ground and VDD in certain points of such a circuit, the circuit comprises a cell () which comprises a flipflop () and means () able to set the output voltage of the cell when the circuit is in the operation mode. These means for setting the output voltage are controlled by a control signal () which depends on the mode signal that indicates whether the signal is in the test mode or in the operation mode.

Cell with fixed output voltage for integrated circuit

A method of discriminating between different types of simulated scan failures includes simulating a scan enable signal to a circuit represented by a netlist corresponding to a scan chain coupled to combinatorial logic being tested, simulating initiation of a data capture cycle in the netlist corresponding to the scan chain, the data capture cycle simulating a series of scan flops from the scan chain being simulated together with the combinatorial logic and simulating scanning data out from each flop in the scan chain and into a test program. The test program extracts the simulated scan flops and graphically displays the simulated scan flops versus time.

Method of discriminating between different types of scan failures, computer readable code to cause a display to graphically depict one or more simulated scan output data sets versus time and a computer implemented circuit simulation and fault detection system

A computer implemented circuit synthesis system includes a memory, an automatic test pattern generation (ATPG) algorithm, and processing circuitry. The memory is configured to provide a database, and is operative to store a netlist including nets of an integrated circuit under design. The automatic test pattern generation (ATPG) algorithm is operative to design and test an integrated circuit design. The processing circuitry is configured to reduce layout area used during scan insertion, and is operative to: a) identify logic registers of a proposed integrated circuit design that are stitched as a shift register; b) use the ATPG algorithm to transform identified logical registers into scan equivalent logical registers; c) stitch scan equivalent logical registers in an order in which the scan equivalent logical registers were stitched; d) identify stitched scan equivalent logical registers having a same net on both an SI port and a D port; and e) replace the stitched scan equivalent logical registers having the same net on both the SI port and D port. A method is also provided for reducing layout area during test insertion when using an ATPG program to design an integrated circuit having design-for-testability features.

Computer implemented circuit synthesis system

Design for test area optimization algorithm

The present invention, generally speaking, provides an integrated circuit testing technique in which hardware accessibility of selected components is exploited in order to avoid scan insertion overhead but achieve as good or better fault coverage than if scan insertion had been used. The term 'pseudo-scan' is used to refer to the use of read and write instructions to achieve the equivalent effect as scan insertion without the addition of scan flops. Existing ATPG tools may be used without modification by performing scan insertion on a 'dummy' circuit and performing ATPG on the scan-augmented dummy circuit. The resulting ATPG vectors are then modified to perform pseudo scan of selected components of the original circuit.

Pseudo-scan testing using hardware-accessible IC structures

A low power scannable asynchronous counter which is fully testable and which consumes low power in a functional mode consists of counter cells cascaded through NOR gate circuits to which clock signals are applied for each of the stages or cells. Each of the stages or cells comprises a flip-flop and a multiplexer which together operate as a toggle flip-flop only when all of the previous flip-flops are set. The result is that the flip-flop clock is forced high preventing any transition of the flip-flop internal clock tree for all stages or cells where the output is low. Thus, no power consumption of such stages takes place during functional operation. In the scan test mode, the counter operates as a shift register and it is fully testable.

Low power scannable counter

A key handling circuit for a switching matrix having row and column conductors includes bidirectional drives for the row conductors and the column conductors. The row drive and the column drive are in a low conductive condition except when a relevant key switch is activated. The row drive provides a current input for the column drive in one phase of operation and the column drive provides a current input for a row drive in a second phase of operation.

Growing community of inventors

Montauroux, France

Laurent Souef