Atmel Corporation

Atmel Rousset S.a.s.

Laurent Paris

Vincent Dupaquis

Yves Fusella

Majid Kaabouch

Stephane Godzinski

Jean-Pascal Maraninchi

Samuel Charbouillot

A subset of software objects stored in a first segment of non-volatile memory are identified as requiring frequent write operations or otherwise associated with a high endurance requirement. The subset of software objects are move to a second segment of non-volatile memory with a high endurance capacity, due to the application of wear leveling techniques to the second segment of non-volatile memory. The first and second segments of memory can be located in the same memory device or different memory devices.

Software adapted wear leveling

A method and system for checking data stored in a memory of in a computer system is disclosed. The memory includes a plurality of memory addresses. The method and system include providing a signature generator coupled with the memory, providing a checker memory coupled with the signature generator and separate from the memory, and providing an address remapper coupled with the checker memory and the memory. The signature generator provides at least one signature corresponding to the data, which resides in a protection window of the memory. The protection window includes at least one memory address of the plurality of memory addresses. The checker memory stores the at least one signature in at least one checker address, which corresponds to the at least one memory address. The address remapper for translates between the at least one memory address and the at least one checker address.

Dynamic redundancy checker against fault injection

A method of operating a multiplication circuit to perform multiply-accumulate operations on multi-word operands is characterized by an operations sequencer that is programmed to direct the transfer of operand segments between RAM and internal data registers in a specified sequence. The sequence processes groups of two adjacent result word-weights (columns), with the multiply cycles within a group proceeding in a zigzag fashion by alternating columns with steadily increasing or decreasing operand segment weights. In multiplier embodiments having additional internal cache registers, these store frequently used operand segments so they aren't reloaded from memory multiple times. In this case, the sequence within a group need not proceed in a strict zigzag fashion, but can jump to a multiply operation involve at least one operand segment stored in a cache.

Efficient multiplication sequence for large integer operands wider than the multiplier hardware

Integrated circuit parallel multiplication circuits, including multipliers that deliver natural multiplication products and multipliers that deliver polynomial products with coefficients over GF(2). A parallel multiplier hardware architecture arranges the addition of partial products so that it begins in a first group of adder stages that perform additions without receiving any carry terms as inputs, and so that addition of the carry terms is deferred until a second group of adder stages arranged to follow the first group. This intentional arrangement of the adders into two separate groups allows both the polynomial product to be extracted from the results of the first group of additions, and the natural product to be extracted from the results of the second group of additions.

Growing community of inventors

Rousset, France

Laurent Paris