Stmicroelectronics S.a.

Stmicroelectronics Gmbh

Stmicroelectronics (rousset) Sas

Laurent Murillo

Philippe Ganivet

François Tailliet

Richard Ferrant

James Leon Worley

François Jacquet

Francois Ricodeau

In an embodiment an electrically erasable programmable readable memory includes a plurality of memory cells organised in a memory plane arranged in a matrix fashion in rows and in columns, wherein each memory cell includes a state transistor having a source region, a drain region, an injection window situated on the side of the drain, a control gate and a floating gate and an isolation transistor having a source region, a drain region and a gate; and an isolation barrier including a buried layer and at least one wall extending from the buried layer to a surface of a substrate, wherein the at least one wall is perpendicular to the buried layer, and wherein the isolating barrier forms an interior substrate surrounding at least one of the memory cells and isolating it from the remainder of the substrate.

Memory architecture for serial EEPROMs

A method for initializing a control device of a memory, the control device executing commands for accessing the memory transmitted to the memory by a control signal, the method comprising steps of detecting the switching on of the memory and of at least partially initializing the control device following the switching on of the memory. According to one embodiment of the present invention, the method comprises steps of detecting a specific event in the control signal, and of at least partially initializing the control device following the detection of the specific event.

Method for initializing a memory

A method for securing a memory area comprising data blocks, wherein at least two control bits are associated with each data block, is provided. The method comprises a step of reading the control bits associated with a current data block intended to be replaced with the new data block, before the writing of a new data block in the memory area. A securing action for securing the memory area is begun if the two control bits have the same value. Upon each write of a new data block in the memory area, control bits having opposite values are written in the memory area. The method may be applied, for example, to the securization of a binary counter.

Method for securing data blocks in an electrically programmable memory

A method for detecting a malfunction in a state machine is described. The state machine has an operation modeled by a set of states linked to each other by transitions, the state machine generating, upon each transition, output signals according to input signals comprising signals generated during a previous transition. During a transition, the method comprises steps of generating at least one control signal according to a control signal generated during a previous transition, determining an expected value of the control signal, and comparing the control signal with the expected value.

Method for detecting a malfunction in a state machine

A method for protecting a state machine having an operation modeled by a set of states linked to each other by transitions, the state machine evaluating output signals upon each transition during an evaluation phase according to input signals comprising signals evaluated during a previous transition, the method comprising steps of determining a minimum duration of each evaluation phase according to a minimum duration to evaluate the output signals according to the input signals, and of adjusting the duration of each evaluation phase.

Method for controlling the evaluation time of a state machine

A matrix H for encoding data words is defined for wide word ECC with uniform density and a reduced number of components. The H-matrix is incorporated in an encode unit operable to Hamming encode a data word with a 10&#xd7;528 matrix generated in groups of four columns wherein; a first column is a complement of a second column; the value of the second column ranges from 9 to 271 in increments of two; a third column is a complement of a fourth column; and the value of the fourth column is the same as the value of the second column less one; and wherein a 528-bit bottom row is added to the 10&#xd7;528 matrix comprising alternating zeroes and ones starting with a zero creating an 11&#xd7;528 matrix.

H-matrix for error correcting circuitry

Error detection and correction codes are provided. For a word of m bits that is to be coded, a vector with m components, each component corresponding to a bit of the word, is formed. The vector is multiplied, using a computing circuit, by a parity control matrix. The parity control matrix includes at least one couple of complementary lines.

High-efficiency error detection and/or correction code

A method for determining r error detection bits that can be associated with a word of m bits to be coded, including the step of calculating the product of a vector with m components representative of the word of m bits to be coded and of a parity control matrix of dimension r&#xd7;m. The parity control matrix is such that each column of matrix includes an odd number of 's' greater than or equal to three. The present invention also relates to a method for determining a syndrome.

A method for determining r error detection bits of a word of m bits to be coded, including the step of calculating the product of a vector with m components representative of the word of m bits to be coded and of a parity control matrix. The parity control matrix includes at least two consecutive complementary columns. The present invention also relates to a method for determining a syndrome, as well as a coding and decoding circuit.

An integrated circuit memory including at least two banks each provided with an array of storage elements having at least one redundancy column and each associated with specific sense amplifiers, a row of input/output buffer circuits common to the memory banks, and for each memory bank, a circuit for assigning the redundancy column to an input/output line connected to one of said buffers. The assigning can be performed, for a line of current rank, towards the columns of preceding rank and towards the columns of following rank.

Memory circuit with shared redundancy

A method for determining r error detection bits of a word of m bits to be coded, including the step of calculating the product of a vector with m components representative of said word of m bits to be coded and of a parity check matrix. The parity check matrix includes a pattern matrix that may be repeated in said parity check matrix, and said pattern being chosen so that a sum modulo 2 of any two columns of said sub-matrix does not give as a result another column of said sub-matrix. Another method determines a syndrome using r error detection bits determined by the above method.

Growing community of inventors

Marseilles, France

Laurent Murillo