Stmicroelectronics (crolles 2) Sas

Stmicroelectronics S.a.

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelctronis (crolles 2) Sas

Laurent-Luc Chapelon

Julien Cuzzocrea

Mohamed Bouchoucha

Pascal Ancey

Lea Di Cioccio

Mickael Fourel

Rachid Taibi

Pierre Morin

Fabrice Casset

Perceval Coudrain

Sandrine Lhostis

Alexis Farcy

Cédrick Chappaz

Philippe Brun

Lionel Cadix

Yacine Felk

Pascal Chausse

An image acquisition device includes an array of color filters and an array of microlenses over the array of color filters. At least one layer made from an inorganic dielectric material is formed between the array of color filters and the array of microlenses.

Image acquisition device

A phase-change memory includes a strip of phase-change material that is coated with a conductive strip and surrounded by an insulator. The strip of phase-change material has a lower face in contact with tips of a resistive element. A connection network composed of several levels of metallization coupled with one another by conducting vias is provided above the conductive strip. At least one element of a lower level of the metallization is in direct contact with the upper surface of the conductive strip.

Phase-change memory

An integrated structure includes a support supporting at least one chip and a heat dissipating housing, attached to the chip. The housing is thermally conductive and has a thermal expansion compatible with the chip. The housing may further including closed cavities filled with a phase change material.

Integrated structure with improved heat dissipation

An integrated circuit chip includes a substrate die and integrated circuits and a layer incorporating a front electrical interconnect network formed on a front face of the substrate die. A local electrical connection via made of an electrically conductive material is formed in a hole of the substrate die. The via is linked to a connection portion of the electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via. A local external protection layer at least partly covers the electrical connection via and the electrical connection pillar.

Integrated circuit chip and fabrication method

A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated circuits and opening onto two locations respectively in electrical contact with the two metallic lines. The cavities may be sized to place a measuring apparatus at the bottom of the cavities, and in electrical contact with the two locations.

Method for estimating the diffusion length of metallic species within a three-dimensional integrated structure, and corresponding three-dimensional integrated structure

An electronic chip including a semiconductor substrate () covered with an insulating layer () including metal interconnection levels () and interconnection pillars () connected to said metal interconnection levels (), said pillars () forming regions () protruding from the upper surface of said insulating layer () and capable of forming an electric contact, wherein said pillars () have a built-in portion () in a housing formed across the thickness of at least said insulating layer ().

Electronic chip comprising connection pillars and manufacturing method

A three-dimensional integrated structure includes a first integrated circuit having a substrate assembled in an interlocking manner with a second integrated circuit having a substrate. The substrate of the first integrated circuit comprises first pores separated by first partitions, and the substrate of the second integrated circuit comprises second pores separated by second partitions. The first partitions interlock with the second pores and the second partitions interlock with the first pores so as to define at least one region bounded by the two substrates. A phase-change material is retained within the at least one region.

Process for fabricating a three-dimensional integrated structure with improved heat dissipation, and corresponding three-dimensional integrated structure

A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.

Stack of semiconductor structures and corresponding manufacturing method

An electrical connection structure for an integrated circuit chip includes a through via provided in a opening and a laterally adjacent void that are formed in a rear face of a substrate die. A front face of the substrate die includes integrated circuits and a layer incorporating a front electrical interconnect network. The via extends through the substrate die to reach a connection portion of the front electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via above the void. A local external protection layer may at least partly cover the electrical connection via and the electrical connection pillar.

An assembly of semiconductor wafers/chips wherein the adjacent surfaces of the two wafers/chips comprise an insulating layer having opposite copper pads inserted therein. The insulating layer is made of a material selected from the group including silicon nitride and silicon carbon nitride.

Chip assembly system

A three-dimensional integrated structure is formed from a first integrated circuit with a first cavity filled with a first conductive material and a second integrated circuit with a second cavity filled with a second conductive material, the second cavity facing the first cavity. The filled first cavity forms a first element and the filled second cavity forms a second element, the first and second elements separated from each other by a cavity. The first and second conductive materials have different thermal expansion coefficients. A contact detection circuit is electrically connected to the filled first and second cavities, and is operable to sense electrical contact between the first and second conductive materials in response to a change in temperature.

Growing community of inventors

Domene, France

Laurent-Luc Chapelon