Centre National De La Recherche Scientifique

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Applied Materials, Inc.

Université Joseph Fourier

Other

Commissariat a L'energie Atomique

Université Grenoble Alpes

Etat Francais, Represente Par Le Ministre Des Pos Tes, Destelecommunicati

Centre National De La Recherche Scientifique-cnrs

Université Joseph Fourier - Grenoble

Laurent J Vallier

Olivier Joubert

Nicolas Posseme

Srinivas D Nemani

Thorsten B Lill

Samer Banna

Lei Lian

Daniel Bensahel

Maxime Darnon

Jean-Michel Hartmann

Jacques Henri Pelletier

Sebastien Barnola

Caroline Hernandez

Pascal Besson

Fran&ccedil;ois Martin

Thibaut David

Yves A Arnal

Virginie Loup

Michel G Pichot

Gilles Cunge

David Fuard

Pierre-Edouard Raynal

Marceline Bonvalot

Giles Cunge

Johann Foucher

Torsten Lill

A substrate is provided with a monocrystalline silicon-germanium layer with a first surface covered by a protective oxide obtained by wet process and having a degradation temperature. The protective oxide is transformed into fluorinated salt which is then eliminated. The substrate is placed in a processing chamber at a lower temperature than the degradation temperature and is subjected to a temperature ramp up to a higher temperature than the degradation temperature. The first surface is annealed in a hydrogen atmosphere devoid of silicon, germanium and precursors of the materials forming the target layer. When the temperature ramp is applied, a silicon precursor is inserted in the processing chamber between a loading temperature and the degradation temperature to deposit a monocrystalline buffer layer. A mono-crystalline target layer is deposited by chemical vapour deposition.

Method for fabricating a monocrystalline structure

The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at least one silicon-based gas mixed with oxygen (O) and/or nitrogen (N) so as to grow a passivation layer all along said etching, at least on flanks of the layer of porous dielectric material and wherein the silicon-based gas is taken from all the compounds of the type SiHfor which the ratio x/y is equal or greater than 0.3 or is taken from all the compounds of the following types: SiFand SiCl, where x is the proportion of silicon (Si) in the gas and y is the proportion of fluorine (F) or chlorine (Cl) or hydrogen (H) in the gas.

Method of etching a porous dielectric material

A method is provided for forming spacers for a gate of a field effect transistor, the gate being situated above a layer of semiconductor material, including forming a layer of nitride covering the gate; modifying the layer by plasma implantation of light ions, having an atomic number equal or less than 10, in the layer in order to form a modified layer of nitride, the modifying being performed so as not to modify the layer of nitride over its entire thickness at flanks of the gate; and removing the modified layer of nitride by a selective wet or dry etching, of the modified layer relative to said layer of semiconductor material and relative to the non-modified layer at the flanks of the gate, without etching the layer of semiconductor material, wherein an entire length of the non-modified layer at the flanks remains after the selective wet or dry etching.

Method for forming spacers for a transistor gate

A microelectronic method for etching a layer to be etched, including: modifying the layer to be etched from a surface of the layer to be etched and over a depth corresponding to at least a portion of thickness of the layer to be etched to form a film, with the modifying including implanting light ions into the layer to be etched; and removing the film includes a selective etching of the film relative to at least one layer underlying the film.

Microelectronic method for etching a layer

The invention relates to the field of production in thin coatings of electronic devices and/or MEMS and relates to an improved method for forming a pattern in a thin SiARC anti-reflective coating, comprising the doping by deposition of such SiARC coating covered with a resist pattern through a protective coating of the resist pattern, then etching the doped zones of the SiARC coating (FIG.).

Method of obtaining patters in an antireflective layer

In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process.

Embedded test structure for trimming process control

Process for making a gate for a short channel CMOS transistor structure

Method for treating a silicon substrate, by nitriding, to form a thin insulating layer

This invention relates to a process for surface treatment of a substrate carried by an electrode and immersed in a sealed engraving or deposition chamber equipped with plasma generating means, of the type involving the application to the electrodes, of a variable voltage, produced by a generator that is independent of the plasma generating means, wherein said process comprises the steps of:

Process for surface treatment by plasma of a substrate supported by an

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Meylan, France

Laurent J Vallier