Micron Technology Incorporated

Laurent Isenegger

Robert Michael Walker

Dhawal Bavishi

Patrick A La Fratta

Cagdas Dirik

Nikesh Agarwal

Jeffrey Frederiksen

Kirthi Ravindra Kulkarni

Jeffrey L Scott

Described apparatuses and methods relate to a write request buffer for a memory system that may support a nondeterministic protocol. A host device and connected memory device may include a controller with a read queue and a write queue. A controller includes a write request buffer to buffer write addresses and write data associated with write requests directed to the memory device. The write request buffer can include a write address buffer that stores unique write addresses and a write data buffer that stores most-recent write data associated with the unique write addresses. Incoming read requests are compared with the write requests stored in the write request buffer. If a match is found, the write request buffer can service the requested data without forwarding the read request downstream to backend memory. Accordingly, the write request buffer can improve the latency and bandwidth in accessing a memory device over an interconnect.

Write request buffer capable of responding to read requests

A request can be provided, from a front-end of a memory sub-system, to a processing device of the memory sub-system and deleting the request from a buffer of the front-end of the memory sub-system. Responsive to deleting the request from the buffer, determining a first quantity of requests in the buffer and responsive to deleting the requests from the buffer, determining a second quantity of outstanding requests in the back-end of the memory sub-system. Responsive to deleting the request from the buffer and providing the request to the processing device, determining whether to provide a response to a host, wherein the response includes an indication of the quantity of requests in the buffer and of outstanding requests in a back-end of the memory sub-system, based on a comparison of the second quantity of outstanding requests to a threshold.

Request control for memory sub-systems

A system includes a processing device that determines whether a memory bank is active and adds an activate command for a row of the memory bank accessed by an oldest command for the memory bank to a command scheduler in response to determining the memory bank is not active. The processing device determines whether the row of the memory bank has a corresponding row command in response to determining the memory bank is active. The processing device determines whether a close page mode is enabled or an open row timer has expired on the row and adds a precharge command to the command scheduler in response to determining the close page mode is enabled or the open row timer has expired. The processing device executes a command in the command scheduler based on a priority of commands included in the command scheduler.

Command scheduling component for memory

A method includes receiving, at a direct memory access (DMA) controller of a memory device, a first command from a first cache controller coupled to the memory device to prefetch first data from the memory device and sending the prefetched first data, in response to receiving the first command, to a second cache controller coupled to the memory device. The method can further include receiving a second command from a second cache controller coupled to the memory device to prefetch second data from the memory device, and sending the prefetched second data, in response to receiving the second command, to a third cache controller coupled to the memory device.

Interleaved cache prefetching

A method includes receiving a write request to a write queue of a host having the write queue and a read queue; initiating a write queue timer upon receiving the write request to the write queue of the host, wherein the write queue timer has a write queue timer expiry threshold value; and executing one or more write requests when the write queue timer reaches the write queue timer expiry threshold value.

Write request thresholding

A request to access data at an address is received from a host system. A tag associated with the address is determined to not be found in first entries in a first content-addressable memory (CAM) or in second entries in a second CAM. Responsive to determining that the tag is not found in the first entries or in the second entries, a particular entry of the first entries that each includes valid data is selected. A determination is made whether the particular entry satisfies a condition indicating that content in the particular entry is to be stored in the second CAM. The content is associated with other data stored in the cache. Responsive to determining that the condition is satisfied, the content of the particular entry is stored in one of the second entries to maintain the data in the cache.

Using a second content-addressable memory to manage memory burst accesses in memory sub-systems

Described apparatuses and methods relate to a memory-flow control register for a memory system that may support a nondeterministic protocol. To help manage the flow of memory requests in a system, a memory device can include logic, such as a hardware register, that can store values indicative of a total number of memory requests that are serviceable by the memory device at a time. The logic can be configured by device manufacturers during assembly. The manufacturers can determine the limits or capabilities of the system, based on the components and structures, and publish the capabilities, including QoS, based on the limits. When the memory device is connected to a host, the host can read the values and limit the number of memory requests sent to the device based on the values. Accordingly, the memory-flow control register can improve latency and bandwidth in accessing a memory device over an interconnect.

Memory-flow control register

A system includes a first controller configured to adjust a count of a number of first transactions and adjust a count of a number of second transactions. The count of the number of first transactions and the count of the number of second transactions are adjusted when a first transaction or second transaction is either received or executed by a second controller. The second controller is coupled to the first controller and is configured to limit the number of first transactions to a particular quantity of outstanding first transactions, limit the number of second transactions to a particular quantity of outstanding second transactions, and limit a number of total transactions to a particular quantity of outstanding total transactions.

Outstanding transaction monitoring for memory sub-systems

A method includes determining a traffic pattern of access requests within a queue or a system, or both and dynamically adjusting, within a particular range, a queue depth of the queue based on the determined traffic pattern of access requests to balance bandwidth and latency associated with executing the access requests.

Dynamic queue depth adjustment

A processing device, operatively coupled with a plurality of memory devices, is configured to receive a DMA command for a plurality of data sectors to be moved from a source memory region to a destination memory region, the destination memory region comprises a plurality of noncontiguous memory addresses and the DMA command comprises a destination value referencing the plurality of noncontiguous memory addresses. The processing device further retrieves the plurality of noncontiguous memory addresses from a location identified by the destination value. The processing device then reads the plurality of data sectors from the source memory region. The processing device also performs, for each respective data sector of the plurality of data sectors associated with the DMA command, a write operation to write the respective data sector into a corresponding respective noncontiguous memory address from the plurality of noncontiguous memory addresses of the destination memory region.

Direct memory access (DMA) commands for noncontiguous source and destination memory addresses

A processing device, operatively coupled with a memory device, is configured to receive a direct memory access (DMA) command to perform a memory access operation, the DMA command comprising a priority value; assign the DMA command to a priority queue of a plurality of priority queues based on the priority value of the DMA command; and execute a plurality of DMA commands from the plurality of priority queues according to a corresponding execution rate of each priority queue of the plurality of priority queues.

Quality of service levels for a direct memory access engine in a memory sub-system

A method is described for managing the issuance and fulfillment of memory commands. The method includes receiving, by a cache controller of a memory subsystem, a first memory command corresponding to a set of memory devices. In response, the cache controller adds the first memory command to a cache controller command queue such that the cache controller command queue stores a first set of memory commands and sets a priority of the first memory command to either a high or low priority based on (1) whether the first memory command is of a first or second type and (2) an origin of the first memory command.

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Morgan Hill, CA, United States of America

Laurent Isenegger