Texas Instruments Corporation

Laurent Ichard

Gilbert Laurenti

Douglas E Deao

Mark L Buser

Jean-Pierre Giacalone

Marc Couvrat

Shigeshi Abiko

Eric L Badi

Armelle Laine

Herve Catan

Karim Djafarian

Vincent Gillet

Alain Boyadjian

Gael Clave

Anne Lombardot

Francois Theodorou

Jean-Marc Philippe Bachot

Yves Masse

Eric Ponsot

Jack Rosenzweig

Walter A Jackson

Jean-Louis Tardieux

Emmanuel Ego

Frederic Nidegger

David Russell

N M Ganesh

Olivier Morchipont

A microprocessor and a method of operating the microprocessor are provided in which a portion of the microprocessor is partitioned into a plurality of partitions. A sequence of instructions is executed within an instruction pipeline of the microprocessor. A block of instructions within the sequence of instructions is repetitively executed in response to a local repeat instruction. Either prior to executing the block of instructions, or during the first iteration of the loop, a determination is made that at least one of the plurality of partitions is not needed to execute the block of instructions. Operation of the at least one identified partition is inhibited during the repetitive execution of the block of instructions in order to reduce power dissipation.

Microprocessor with selected partitions disabled during block repeat

A processor ( ) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit ( ), a program flow control unit ( ), an address/data flow unit ( ), a data computation unit ( ), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit ( ) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.

Microprocessors

Growing community of inventors

Cagnes sur Mer, France

Laurent Ichard