International Business Machines Corporation

Laurent Fournier

Avi Ziv

Itai Jaeger

Michal Rimon

Anatoly Koyfman

Sigal Asaf

Alon Gluska

Allon Adir

Raanan Gewirtzman

Yossi Malka

Ofer Peled

Aharon Aharon

Steven Mittermaier

Yossi Lichtenstein

Alion Adir

Shai Rubin

Reuven Nisser

A method, apparatus and product to be used in verification. The method comprising: based on a test generation input that defines a plurality of requirements automatically determining a mutated test generation input, wherein the mutated test generation input defining a mutated requirement which is absent from the test generation input, wherein the mutated requirement is based on a requirement of the plurality of requirements and contradicts, at least in part, the plurality of requirements; and generating one or more test-cases based on the mutated test generation input, whereby the one or more test-cases violate at least one requirement of the test generation input.

Mutations on input for test generation

Coverage analysis may be performed using reverse time. The coverage analysis may be based on last hit data. The last hit data may comprise a timestamp indicating a last time in which a coverage event was covered. Utilizing last hit data instead of first hit data as is known in the art enables distinction between coverage goals that were never covered and coverage goals that were not covered lately.

Using reverse time for coverage analysis

A Design-Under-Test (DUT) may be designed to perform speculative execution of a branch path prior to determination whether the branch path is to be performed. Verification of the operation of DUT in respect to the speculative execution is disclosed. A template may be used to generate a plurality of tests. In addition to standard randomness of the tests to various parameters in accordance with the template, the tests may also differ in their respective speculative execution paths. The tests are partitioned by a generator into portions to be placed in speculative paths and portions to be placed in non-speculative paths. The generator may provide for a variance in portions. The generator may provide for nested speculative paths.

Verification of speculative execution

A parametrically controlled model-based test generator automatically generates architectural compliance test suites for different implementations of a processor architecture, based on a set of architectural decisions chosen among optional behaviors for each implementation. Thus, different implementations of the same architecture can be easily supported by modifying the parameter values. In addition, ongoing changes to the architecture or comprehensive updates to the test suite can be easily handled by updating the architecture model or the coverage models, forgoing the need to review the whole, potentially huge, set of tests.

Automatic generation of test suite for processor architecture compliance

Functional coverage techniques during design verification using cross-product coverage models and hole analysis are enhanced by the use of coverage queries. After running a test suite, a core set of non-covered events is specified. A coverage query is then automatically constructed and executed on the test results to identify a hole in the functional coverage that satisfies conditions of the coverage query and includes the core set. The results of the query are presented as a simplified view of the coverage of the events in the cross-product space. Use of coverage queries allows a verification team to focus on specific areas of interest in the coverage space and to deal practically with highly complex coverage models. It also avoids the burden of producing and evaluating complete hole analysis reports.

Hole query for functional coverage analysis

Methods and systems are presented for generation of a test suite in order to validate compliance of a process with its process specification. The methodology involves a formal description of the process using a flowchart, refinement of the flowchart to include misinterpretations of the process specification, defining compliance coverage models over the flowchart, and automatically generating test case scenarios that cover the models. Internal and external types of misinterpretation are distinguished. A compliance test suite is automatically generated and observations made of the details of the traversal through the flow chart when the tests are executed.

Systematic compliance checking of a process

A method for functional verification of a design for a parallel processing device includes receiving a sequence of single instructions from a dynamic test program generator, and assembling a plurality of the instructions from the sequence into an instruction word, in accordance with predetermined rules applicable to the parallel processing device. The instruction word is input to a simulator of the parallel processing device so as to determine a response of the device to the instruction word.

Dynamic test program generator for VLIW simulation

A tool for implementing a Floating-Point related application. The tool includes a receiver for receiving a list of commands in a computer language. The language defines Floating-Point events of interest and the regrouping of events into a coverage model in respect of a desired FP instruction. The coverage model has the form of a sequence of Floating-Point commands with constraints on the input operands, intermediate result operand and the result operand. The constraints are expressed in terms of sets that define allowable Floating-Point numbers. The tool further includes a parser for parsing the commands and a processor for processing the parsed commands for realizing on the basis of the events and the coverage model the Floating-Point related application.

Tool for implementing Floating-Point related applications using customized language

A technique that applies the task coverage exercised within a behavioral model of the design to the design itself, while simulating one or more test sequences. Since the behavior model is an accurate and complete program representation of the architectural specification of the hardware design, the test case coverage of the architecture is implied by the measurement of how well the behavioral model code has been exercised. The completeness of the coverage is determined by the test coverage criteria selected, including, for example, statement coverage, branch coverage, or path coverage. The more detailed the criteria, the greater the number of tests.

Method for measuring architectural test coverage for design verification

A method for the automatic verification of external interrupts in modern processor architectures under a very wide range of instruction sequences provides almost complete expected results from each of the involved interrupts. In particular, the method allows the verification of the architectural aspects to the external interrupt mechanism in pipelined and super scalar microprocessors. The method which is based on the assumption that when an external interrupt is serviced, the processor branches to a specific address according to the type of the external interrupt. The first step in the method is a preparation step wherein the memory addresses already used by the test are scanned and unused memory spaces are allocated for a plurality of memory blocks and two memory addresses for pointers. These two addresses are used to find the next block to fill. After this initial preparation step, the interrupt is presented in any desired location by the design simulator controller. Next, the instruction range in which the external interrupt could be serviced is found. External interrupt routines are added to the test. These routines are executed each time the appropriate external interrupt is served by the processor. Finally, the reference model of the processor is used to recompute the expected results of the test. In this process, each external interrupt will update its unique block of memory and, as a result, if the processor sets any of these resources to an incorrect value while servicing any of the external interrupts presented in the test, it will be detected as the actual results of the test will be different than those expected in the test program. A mask is used to detect latency violations. The value saved in memory is independent of the actual timing of the interrupt since all the unknown bits are reset by the mask. By using an offset, the chances of detection of a latency violation are improved.

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Givat Ela, Israel

Laurent Fournier