Commissariat a L'energie Atomique

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelectronics S.a.

Centre National De La Recherche Scientifique

S.o.i.tec Silicon on Insulator Technologies

Institut Polytechnique De Grenoble

S.o.i. Tec Silicon on Insulator Technologies, S.a.

Laurent Clavelier

Chrystel Deguet

Bernard Diem

Franck Fournel

Emmanuel Defay

Vincent Larrey

Jean-Francois Damlencourt

Maud Vinet

Yves Morand

Thomas Signamarcheix

Emmanuel Augendre

Perrine Batude

Cyrille Le Royer

Marc Rabarot

Francois Perruchot

Olivier Faynot

François Perruchot

Hubert Moriceau

Chantal Arena

Philippe Robert

Olivier Thomas

Simon Deleonibus

Thierry Poiroux

Jean-Charles Barbe

Alexandre Reinhardt

Julie Widiez

Jean-Pierre Joly

Patrick Leduc

Jean-Sebastien Moulet

François Andrieu

Jean-Christophe Crebier

Marie-Anne Jaud

Benjamin Vincent

Marek Kostrzewa

Yvan Avenas

Gerard Billiot

Jérôme Dechamp

Jean-Sébastien Moulet

Jean-François Damlencourt

Kremena Vladimirova

Benoit Vianay

François Templier

Frédéric Mayer

The invention provides a method of fabricating an electromechanical structure presenting a first substrate including a layer of monocrystalline material covered in a sacrificial layer that presents a free surface, the structure presenting a mechanical reinforcing pillar in the sacrificial layer, the method including etching a well region in the sacrificial layer to define a mechanical pillar; depositing a first functionalization layer of the first material to at least partially fill the well region and cover the free surface of the sacrificial layer around the well region; depositing a second material different from the first material for terminating the filling of the well region to thereby cover the first functionalization layer around the well region, planarizing the filler layer, the pillar being formed by the superposition of the first material and second material in the well region; and releasing the electromechanical structure by removing at least partially the sacrificial layer.

Method of fabricating an electromechanical structure including at least one mechanical reinforcing pillar

An acoustic wave device comprising at least one surface acoustic wave filter and one bulk acoustic wave filter, the device including, on a substrate comprising a second piezoelectric material: a stack of layers including a first metal layer and a layer of a first monocrystalline piezoelectric material, wherein the stack of layers is partially etched so as to define a first area in which the first and second piezoelectric materials are present and a second area in which the first piezoelectric material is absent; a second metallization at the first area for defining the bulk acoustic wave filter integrating the first piezoelectric material, and a third metallization at the second area for defining the surface acoustic wave filter integrating the second piezoelectric material.

Acoustic wave device including a surface wave filter and a bulk wave filter, and method for making same

A method for producing an emissive pixel screen includes forming an active pixel matrix along which an electrode forming layer runs and having pixels arranged according to a distribution, forming an anisotropic substrate that includes a set of light emitting diodes constituted by parallel nanowires and arranged in an insulating matrix transversely with respect to a substrate thickness and having a density higher than a density of the pixels irrespective of the pixel distribution, connecting the substrate to the active pixel matrix by connecting only sub-groups of the parallel nanowires by a first end to separate pixel electrodes defined in the electrode forming layer according to the distribution of the pixels in the matrix, and connecting the sub-groups, by another end, to a common electrode, and delimiting the sub-groups by rendering the nanowires of the substrate that are arranged between the sub-groups emissively inactive.

Method for manufacturing a very-high-resolution screen using a nanowire-based emitting anisotropic conductive film

A field effect transistor including: a support layer, a plurality of active zones based on a semiconductor, each active zone configured to form a channel and arranged between two gates adjacent to each other and consecutive, the active zones and the gates being arranged on the support layer, each gate including a first face on the side of the support layer and a second face opposite the first face. The second face of a first of the two gates is electrically connected to a first electrical contact made on the second face of the first of the two gates, and the first face of a second of the two gates is electrically connected to a second electrical contact passing through the support layer. The gates of the transistor are not electrically connected to each other.

Field effect transistor with alternate electrical contacts

An integrated circuit including at least: a first MOS transistor; a second MOS transistor, arranged on the first MOS transistor, the second MOS transistor including a channel region in at least one semiconductor layer including two approximately parallel primary faces; a portion of at least one electrically conductive material electrically connected to a gate of the first transistor and arranged between the gate of the first transistor and the channel region of the second transistor; a dielectric layer arranged at least between the portion of the electrically conductive material and the channel region of the second transistor; and a section of the channel region of the second transistor in a plane parallel to the two primary faces of the semiconductor layer is included in a section of the portion of the electrically conductive material projected in said plane.

Integrated circuit with electrostatically coupled MOS transistors and method for producing such an integrated circuit

A method of producing a hybrid substrate includes preparing a monocrystalline first substrate to obtain two surface portions. A temporary substrate is prepared including a mixed layer along which extends one surface portion and is formed of first areas and adjacent different second areas of amorphous material, the second areas forming at least part of the free surface of the first substrate. The first substrate is bonded to the other surface portion with the same crystal orientation as the first surface portion, by molecular bonding over at least the amorphous areas. A solid phase recrystallization of at least part of the amorphous areas according to the crystal orientation of the first substrate is selectively carried and the two surface portions are separated.

Method of producing a hybrid substrate by partial recrystallization of a mixed layer

An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.

Method of adjusting the threshold voltage of a transistor by a buried trapping layer

The invention relates to an electronic chip, comprising: a semiconductor substrate () having an active area () formed by at least one P doped region and at least one N doped region which form one or more P-N junctions through which most of the useful current flows when said electronic chip is in a conductive state, and at least one channel () through which a heat transport coolant can flow, the channel(s) passing through at least said P or N doped region of the active area. Each channel () is rectilinear and passes through the substrate () in a direction which is collinear with a direction F to the nearest &#xb1;45&#xb0;, where the direction F is perpendicular to the plane of the substrate.

Electronic chip having channels through which a heat transport coolant can flow, electronic components and communication arm incorporating said chip

A method for making a thin-film element includes epitaxially growing a first crystalline layer on a second crystalline layer of a support where the second crystalline layer is a material different from the first crystalline layer, the first crystalline layer having a thickness less than a critical thickness. A dielectric layer is formed on a side of the first crystalline layer opposite to the support to form a donor structure. The donor structure is assembled with a receiver layer and the support is removed.

Method for making a thin-film element

A process for forming a thin film of a given material includes providing a first substrate having, on the surface, an amorphous and/or polycrystalline film of the given material and a second substrate is bonded to the first substrate by hydrophobic direct bonding (molecular adhesion), the second substrate having a single-crystal reference film of a given crystallographic orientation on the surface thereof. A heat treatment is applied at least to the amorphous and/or polycrystalline film, where the heat treatment causes at least a portion of the amorphous and/or polycrystalline film to undergo solid-phase recrystallization along the crystallographic orientation of the reference film, where the reference film acts as a recrystallization seed. The at least partly recrystallized film is then separated from at least a portion of the reference film.

Method in the microelectronics fields of forming a monocrystalline layer

A data storage medium includes a carrier substrate having an electrode layer on the surface thereof and a sensitive material layer extending along the electrode layeradapted to be locally modified between two electrical states by the action of a localized electric field. A reference plane extends globally parallel to the sensitive material layer and is configured to accommodate at least one element for application of an electrostatic field in combination with the electrode layer the electrode layer including a plurality of conductive portions having a dimension at most equal to 100 nm in at least one direction parallel to the reference plane and separated by at least one electrically insulative zone, where at least some of the conductive portions are electrically interconnected, the conductive portions defining data write/read locations within the sensitive material layer.

Data storage medium and associated method

A method for producing a hybrid substrate includes preparing a first substrate including a mixed layer and an underlying electrically insulating continuous layer, the mixed layer made up of first single-crystal areas and second adjacent amorphous areas, the second areas making up at least part of the free surface of the first substrate. A second substrate is bonded to the first substrate, the second substrate including on the surface thereof, a reference layer with a predetermined crystallographic orientation. The first substrate is bonded to the second substrate by hydrophobic molecular bonding of at least the amorphous areas. A recrystallization of at least part of the amorphous areas to solid phase is carried out according to the crystallographic orientation of the reference layer, and the two substrates are separated at the bonding interface.

Method of producing a hybrid substrate having a continuous buried electrically insulating layer

A method for making a stack of at least two stages of circuits, each stage including a substrate and at least one component and metallic connections formed in or on this substrate, the assembly of a stage to be transferred onto a previous stage including: a) ionic implantation in the substrate of the stage to be transferred through at least part of the components, so as to form a weakened zone, b) formation of metallic connections of the components, c) transfer and assembly of some of this substrate onto the previous stage, and d) a step to thin the transferred part of the substrate by fracture along the weakened zone.

Method for transferring chips onto a substrate

A microelectronic device including: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transistor including a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by an insulating zone, and said insulating zone being constituted of several different dielectric materials include a first dielectric material and a second dielectric material.

Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT

The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.

Epitaxial methods for reducing surface dislocation density in semiconductor materials

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Grenoble, France

Laurent Clavelier