Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelectronics (crolles 2) Sas

Laurent Brunet

Perrine Batude

Nicolas Posseme

Claire Fenouillet-Beranger

Xavier Garros

Maud Vinet

Frank Fournel

Lamine Benaissa

Francois Andrieu

Fabien Deprat

Fabrication of a circuit with superposed transistors includes assembly of a structure having transistors formed from a first semiconducting layer with a support provided with a second semiconducting layer in which transistors are provided on a higher level. The second semiconducting layer is coated with a thin layer of silicon oxide. The assembly of said structure and the support is made by direct bonding in which the thin silicon oxide layer is bonded to oxidised portions of getter material.

Assembly for 3D circuit with superposed transistor levels

A method is provided for forming a transistor from a stack including the following successive layers: an electrically insulating layer, an active zone including at least one semiconductor layer, and a gate, sides of which are configured to be covered by at least one spacer, the method including: a phase of forming lateral cavities; and forming a raised drain and a raised source that fill the lateral cavities by growing the semiconductor layer via epitaxy, the forming of the lateral cavities includes, after a step of partially removing the semiconductor layer: forming a sacrificial layer, partially removing the sacrificial layer; forming spacers against the sides of the gate resting on a residual sacrificial layer; and totally removing the residual sacrificial layer in order to form the lateral cavities.

Method of manufacturing a dopant transistor located vertically on the gate

A process for fabricating a transistor structure produced sequentially, comprises at least one string of the following steps: producing at least one first transistor from a first semiconductor layer possibly made of silicon; encapsulating at least the first transistor with at least one first dielectric layer defining a first assembly; bonding a second dielectric layer located on the surface of a second semiconductor layer possibly made of silicon, to the first dielectric layer; depositing a planarizing material layer on the surface of the second semiconductor layer; selectively etching the planarizing material layer, to the second semiconductor layer; and producing at least one second transistor from the second semiconductor layer.

Process for fabricating a transistor structure including a plugging step

A method of fabrication of an integrated circuit is provided, including: providing a substrate including a first active layer and a first metallic level of interconnection arranged on top of the active layer and including first lines of interconnection separated by a first filling of sacrificial material; forming a superposition of an insulator layer and second lines of interconnection; providing access to the first filling through the insulator layer; filling the provided access with a second filling of sacrificial material; forming a second active layer on top of the second metallic level of interconnection; providing access to the second filling through the second active layer; and removing the first and the second fillings by a chemical etching through the provided access to the second filling.

Integrated circuit having a plurality of active layers and method of fabricating the same

This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device, a dielectric layer, and a first semiconductor layer; b) providing a second structure successively including a substrate, an active layer, a dielectric layer, and a second semiconductor layer, the active layer being designed to form an electronic device; c) bonding the first and second structures by direct bonding between the first and second semiconductor layers so as to form a bonding interface; d) removing the substrate of the second structure so as to expose the active layer; e) introducing dopants into the first and second semiconductor layers so as to form a ground plane.

Fabrication method of a stack of electronic devices

A method for measuring the changes of the electrical performance of an FDSOI transistor between a first and a second state of the transistor after an operating period t, including the following steps:

Method and device for measuring changes over time of the electrical performance of an FDSOI transistor

A method for evaluating the electric performances of an FDSOI transistor, including the steps of: measuring capacitance and/or conductance of the FDSOI transistor, by applying a voltage V&#x3e;0 on a substrate composed of semiconductor of the FDSOI transistor when the FDSOI transistor is NMOS or a voltage V&#x3c;0 on the substrate composed of semiconductor of the FDSOI transistor when the FDSOI transistor is PMOS, depending on a voltage Vapplied between a gate and source and drain regions of the FDSOI transistor.

Growing community of inventors

Grenoble, France

Laurent Brunet