Texas Instruments Corporation

Laurent A Six

Armelle Laine

Daniel Mazzocco

Gerald Ollivier

A method for providing context save and restore using a test scan chain is provided. The method includes dividing a scan chain () of digital logic components () into a plurality of sub-chains (). A first data set is provided in the sub-chains (). The sub-chains () are linked in parallel and to a hardware resource for executing an application. The sub-chains () are linked to a device memory (). A first application is executed to update the first data set in the sub-chains (). The first application is operable to use the hardware resource. The updated first data set is stored in the device memory (). A second data set is restored from the device memory () to the sub-chains (). A second application is executed to update the second data set in the sub-chains (). The second application is operable to use the hardware resource.

Context save and restore using test scan chains

A digital system is provided with a memory () that can be shared by two or more data requestors (). Two modes of access are provided. In a shared access memory (SAM) access mode, all of the data requestors can sequentially access the memory. In a host only memory (HOM) access mode, a portion () of the memory is connected directly to one of the requestors, such, as a host processor (), so that high bandwidth transfers can be performed. A portion () that is not selected to be in HOM mode can be accessed by other requestors or shut down to save power. The size (S1) of the portion of memory selected for HOM mode is selected to match the requirements of a given application and can be changed by writing a size value to a register.

Shared memory with programmable size

A digital system is provided with a multi-channel DMA controller ( ) for transferring data between various resources ( ). Each channel includes a source port ( ), a channel controller ( ) and a destination port ( ). Channel to port buses (CP -CP ) are representative of parallel buses that are included in the read address bus (RA). Similar parallel buses are provided for a write address bus and a data output bus, not shown. Port to channel buses (PC -PC ) are representative of parallel buses that are included in data input bus DI. Scheduling circuitry ( ) includes request allocator circuitry, interleaver circuitry and multiplexer circuitry and selects one of the channel to port buses to be connected to an associated port controller ( ) on each clock cycle for providing an address for a transaction performed on each clock cycle. The schedulers operate in parallel and source/destination channel addresses are transferred in parallel to each scheduler via the parallel channel to port buses. Input/output data words are also transferred in parallel to/from each port. Each port is tailored to provide an access protocol required by its associated resource. The ports may be tailored to provide an access protocol required by a different type of resource. Channel and scheduling circuitry within a sub-portion ( ) of the DMA controller can interact with various versions of tailored ports without being modified.

Multi-channel DMA with scheduled ports

A digital system is provided with a memory ( ) that can be shared by two or more data requestors ( ). Two modes of access are provided. In a shared access memory (SAM) access mode, all of the data requestors can sequentially access the memory. In a host only memory (HOM) access mode, the memory is connected directly to one of the requestors, such as a host processor ( ), so that high bandwidth transfers can be performed. The HOM access mode is entered when a priority assigned to the host processor is set to be higher than a priority assigned to any other requester. Registers for holding the priority assignments can be written by at least one of the requesters.

Growing community of inventors

Le Bar sur Loup, France

Laurent A Six